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公开(公告)号:US20220083241A1
公开(公告)日:2022-03-17
申请号:US16948426
申请日:2020-09-17
发明人: Luca Nubile , Ali Mohammadzadeh , Biagio Iorio , Walter Di Francesco , Yuanhang Cao , Luca De Santis , Fumin Gu
IPC分类号: G06F3/06
摘要: A memory device includes a plurality of memory dies, each memory die of the plurality of memory dies comprising a memory array and control logic. The control logic comprises a plurality of processing threads to execute memory access operations on the memory array concurrently, a thread selection component to identify one or more processing threads of the plurality of processing threads for a power management cycle of the associated memory die and a power management component to determine an amount of power associated with the one or more processing threads and request the amount of power during the power management cycle.