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公开(公告)号：US20220122665A1
公开(公告)日：2022-04-21
申请号：US17542562
申请日：2021-12-06
摘要： Memory devices might include a plurality of memory cell pairs each configured to be programmed to store a digit of data; and control circuitry configured to cause the memory device to compare the stored digit of data of each memory cell pair to a received digit of data, determine whether a match condition or a no-match condition is indicated between the stored digit of data of each memory cell pair and the received digit of data, and deem a match condition to be met between the received digit of data and the stored digits of data of the plurality of memory cell pairs in response to a match condition being determined for a majority of memory cell pairs of the plurality of memory cell pairs.
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公开(公告)号：US20220100760A1
公开(公告)日：2022-03-31
申请号：US17033332
申请日：2020-09-25
发明人： Luca De Santis
IPC分类号： G06F16/2453 , G06F16/2455 , G06F16/22 , G06F16/248 , G06F12/02 , G06F12/0882 , G06F11/10
摘要： The present disclosure includes apparatuses and methods for acceleration of data queries in memory. A number of embodiments include an array of memory cells, and processing circuitry configured to receive, from a host, a query for particular data stored in the array, execute the query, and send only the particular data to the host upon executing the query.
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公开(公告)号：US20220083241A1
公开(公告)日：2022-03-17
申请号：US16948426
申请日：2020-09-17
发明人： Luca Nubile , Ali Mohammadzadeh , Biagio Iorio , Walter Di Francesco , Yuanhang Cao , Luca De Santis , Fumin Gu
IPC分类号： G06F3/06
摘要： A memory device includes a plurality of memory dies, each memory die of the plurality of memory dies comprising a memory array and control logic. The control logic comprises a plurality of processing threads to execute memory access operations on the memory array concurrently, a thread selection component to identify one or more processing threads of the plurality of processing threads for a power management cycle of the associated memory die and a power management component to determine an amount of power associated with the one or more processing threads and request the amount of power during the power management cycle.
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公开(公告)号：US20210312994A1
公开(公告)日：2021-10-07
申请号：US17348108
申请日：2021-06-15
发明人： Luca De Santis
摘要： Apparatus including an array of memory cells, and a controller configured to cause the apparatus to determine a first value indicative of a number of memory cells of a plurality of memory cells that are activated in response to a control gate voltage having a particular voltage level, compare the first value to a plurality of second values, and determine an expected data age of the plurality of memory cells or a plurality of read voltages in response to the comparison of the first value to the plurality of second values.
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公开(公告)号：US20210090656A1
公开(公告)日：2021-03-25
申请号：US17111721
申请日：2020-12-04
发明人： Umberto Minucci , Tommaso Vali , Fernanda Irrera , Luca De Santis
摘要： A method can include applying a first voltage to a first memory cell to activate the first memory cell, applying a second voltage to a second memory cell coupled in series with the first memory cell to activate the second memory cell so that current flows through the first and second memory cells, and generating an output responsive to the current. The first voltage and a threshold voltage of the second memory cell can be such that the current is proportional to a product of the first voltage and the threshold voltage of the second memory cell.
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公开(公告)号：US10923200B2
公开(公告)日：2021-02-16
申请号：US16745514
申请日：2020-01-17
摘要： Methods of operating a memory, as well as memory configured to perform such method, include applying an intermediate read voltage to a selected access line for a read operation, adding noise to a sensing operation while applying the intermediate read voltage, determining a value indicative of a number of memory cells of a plurality of memory cells connected to the selected access line that are activated in response to applying the intermediate read voltage to the selected access line, and determining a plurality of read voltages for the read operation in response to the value indicative of the number of memory cells of the plurality of memory cells that are activated in response to applying the intermediate read voltage to the selected access line.
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公开(公告)号：US10776362B2
公开(公告)日：2020-09-15
申请号：US16113055
申请日：2018-08-27
发明人： Luca De Santis , Giulio G. Marotta , Marco-Domenico Tiburzi , Tommaso Vali , Frankie F. Roohparvar , Agostino Macerola
IPC分类号： G06F3/06 , G06F16/2455 , G11C16/06 , G11C7/10 , G11C15/04 , G11C16/04 , G06F7/20 , G06F12/0802 , G11C29/50
摘要： Memory devices for facilitating pattern matching and having an array of memory cells, a plurality of key registers to store a representation of a key word, and a plurality of multiplexers, each multiplexer of the plurality of multiplexers to select a representation of a bit from a key register of the plurality of key registers to compare to data stored in the array of memory cells.
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公开(公告)号：US10712960B2
公开(公告)日：2020-07-14
申请号：US16166231
申请日：2018-10-22
摘要： Memory devices, and methods of operating similar memory devices, include an array of memory cells comprising a plurality of access lines each configured for biasing control gates of a respective plurality of memory cells of the array of memory cells, wherein the respective plurality of memory cells for one access line of the plurality of access lines is mutually exclusive from the respective plurality of memory cells for each remaining access line of the plurality of access lines, and a controller having a plurality of selectively-enabled operating modes and configured to selectively operate the memory device using two or more concurrently enabled operating modes of the plurality of selectively-enabled operating modes for access of the array of memory cells, with each of the enabled operating modes of the two of more concurrently enabled operating modes utilizing an assigned respective portion of the array of memory cells.
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9.发明申请公开(公告)号：US20190341115A1
公开(公告)日：2019-11-07
申请号：US16515134
申请日：2019-07-18
摘要： Memory having an array of memory cells and a controller for access of the array of memory cells that is configured to generate a data value indicative of a level of a property sensed from a data line while applying potentials to control gates of memory cells of more than one string of series-connected memory cells connected to that data line.
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公开(公告)号：US10423350B2
公开(公告)日：2019-09-24
申请号：US15532886
申请日：2017-01-23
发明人： Sivagnanam Parthasarathy , Terry M. Grunzke , Lucia Botticchio , Walter Di Francesco , Vamshi K. Indavarapu , Gianfranco Valeri , Renato C. Padilla , Ali Mohammadzadeh , Jung Sheng Hoei , Luca De Santis
IPC分类号： G06F3/06 , G06F12/02 , G06F12/1009
摘要： The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.
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