公开(公告)号：US20230335179A1

公开(公告)日：2023-10-19

申请号：US17659405

申请日：2022-04-15

Applicant: Micron Technology, Inc.

Inventor： Martin Brox ,  C. Omar Benitez ,  Johnathan L. Gossi ,  Christopher John Kawamura

IPC: G11C11/408 ,  G11C11/4094 ,  G11C11/22

CPC classification number: G11C11/4085 ,  G11C11/4094 ,  G11C11/2259 ,  G11C11/221

Abstract: Methods, systems, and devices for techniques for generating access line voltages are described. A system may use a first voltage supply and a second voltage supply that is configured to supply a lower voltage than the first voltage supply. The system may activate a first circuit to couple a node with the first voltage supply so that a first voltage develops on the node from the first voltage supply. The system may activate a second circuit to couple the node with the second voltage supply so that a second voltage that is lower than the first voltage develops on the node from the second voltage supply.

公开(公告)号：US20200227109A1

公开(公告)日：2020-07-16

申请号：US16732018

申请日：2019-12-31

Applicant: Micron Technology, Inc.

Inventor： Christopher John Kawamura

IPC: G11C11/22 ,  G11C11/56

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. In some examples, multi-level accessing, sensing, and other operations for ferroelectric memory may be based on sensing multiple charges, including a first charge associated with a dielectric of the memory cell and a second charge associated with a polarization of the memory cell. In some cases, multi-level accessing, sensing, and other operations may be based on transferring a first charge associated with a dielectric of the memory cell to a sense amplifier, isolating the sense amplifier, activating the sense amplifier, transferring a second charge associated with a polarization of the memory cell to the sense amplifier, and activating the sense amplifier a second time.

公开(公告)号：US10607677B2

公开(公告)日：2020-03-31

申请号：US16183021

申请日：2018-11-07

Applicant: Micron Technology, Inc.

Inventor： Scott James Derner ,  Christopher John Kawamura

IPC: G11C11/22 ,  G11C7/14

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be initialized to a first state and a second ferroelectric memory cell may be initialized to a different state. Each state may have a corresponding digit line voltage. The digit lines of the first and second ferroelectric memory cells may be connected so that charge-sharing occurs between the two digit lines. The voltage resulting from the charge-sharing between the two digit lines may be used by other components as a reference voltage.

公开(公告)号：US20200066321A1

公开(公告)日：2020-02-27

申请号：US16675021

申请日：2019-11-05

Applicant: Micron Technology, Inc.

Inventor： Scott James Derner ,  Christopher John Kawamura ,  Charles L. Ingalls

IPC: G11C11/22

Abstract: Methods, systems, and apparatuses related to a reprogrammable non-volatile latch are described. A latch may include ferroelectric cells, ferroelectric capacitors, a sense component, and other circuitry and components related to ferroelectric memory technology. The ferroelectric latch may be independent from (or exclusive of) a main ferroelectric memory array. The ferroelectric latch may be positioned anywhere in the memory device. In some instances, a ferroelectric latch may be positioned and configured to be dedicated to single piece of circuitry in the memory device.

公开(公告)号：US10372566B2

公开(公告)日：2019-08-06

申请号：US15267817

申请日：2016-09-16

Applicant: Micron Technology, Inc.

Inventor： Christopher John Kawamura ,  Scott James Derner ,  Charles L. Ingalls

IPC: G06F11/00 ,  G06F11/20 ,  G11C11/22 ,  G06F11/10 ,  G11C29/52

Abstract: Methods, systems, and apparatuses for storing operational information related to operation of a non-volatile array are described. For example, the operational information may be stored in a in a subarray of a memory array for use in analyzing errors in the operation of memory array. In some examples, an array driver may be located between a command decoder and a memory array. The array driver may receive a signal pattern used to execute an access instruction for accessing non-volatile memory cells of a memory array and may access the first set of non-volatile memory cells according to the signal pattern. The array driver may also store the access instruction (e.g., the binary representation of the access instruction) at a non-volatile subarray of the memory array.

公开(公告)号：US10236049B2

公开(公告)日：2019-03-19

申请号：US15979178

申请日：2018-05-14

Applicant: Micron Technology, Inc.

Inventor： Christopher John Kawamura

IPC: G11C11/22

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory device may leverage non-volatile memory properties of a ferroelectric capacitor—e.g., that a ferroelectric capacitor may remain polarized at one of two states without a voltage applied across the ferroelectric capacitor—to activate a subset of sensing components corresponding to multiple memory cells with a common word line. For example, a first and second set of memory cells with a common word like may be selected for a read operation. A first set of sensing components corresponding to the first set of memory cells may be activated for the read operation, and a second set of sensing components that correspond to the second set of memory cells may be maintained in a deactivated state.

公开(公告)号：US10163480B1

公开(公告)日：2018-12-25

申请号：US15662002

申请日：2017-07-27

Applicant: Micron Technology, Inc.

Inventor： Christopher John Kawamura ,  Scott James Derner

IPC: G11C5/10 ,  G11C11/22 ,  G11C11/4074 ,  H01L27/108 ,  H01L27/11507 ,  H01L23/528 ,  G11C11/408

Abstract: Methods, systems, and devices for periphery fill and localized capacitance are described. A memory array may be fabricated with certain containers connected to provide capacitance rather than to operate as memory cells. For example, a memory cell having one or two transistors, or other switching components, and one capacitor, such as a ferroelectric or dielectric capacitor, may be electrically isolated from one or more containers sharing a common access line, and the isolated containers may be used as capacitors. The capacitors may be used for filtering in some examples. Or the capacitance may be used to boost or regulate voltage in, for example, support circuitry.

公开(公告)号：US20180158502A1

公开(公告)日：2018-06-07

申请号：US15844145

申请日：2017-12-15

Applicant: Micron Technology, Inc.

Inventor： Scott James Derner ,  Christopher John Kawamura ,  Charles L. Ingalls

IPC: G11C11/22

CPC classification number: G11C11/2275 ,  G11C11/221 ,  G11C11/2273

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first value may be written to a first memory cell and a second value may be written to a second memory cell. Each value may have a corresponding voltage when the memory cells are discharged onto their respective digit lines. The voltage on each digit line after a read operation may be temporarily stored at a node in electronic communication with the respective digit line. A conductive path may be established between the nodes so that charge sharing occurs between the nodes. The voltage resulting from the charge sharing may be used to adjust a reference voltage that is used by other components.

公开(公告)号：US09990977B2

公开(公告)日：2018-06-05

申请号：US15636344

申请日：2017-06-28

Applicant: Micron Technology, Inc.

Inventor： Christopher John Kawamura

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2253 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/2275 ,  G11C11/2297

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory device may leverage non-volatile memory properties of a ferroelectric capacitor—e.g., that a ferroelectric capacitor may remain polarized at one of two states without a voltage applied across the ferroelectric capacitor—to activate a subset of sensing components corresponding to multiple memory cells with a common word line. For example, a first and second set of memory cells with a common word like may be selected for a read operation. A first set of sensing components corresponding to the first set of memory cells may be activated for the read operation, and a second set of sensing components that correspond to the second set of memory cells may be maintained in a deactivated state.

公开(公告)号：US20180102158A1

公开(公告)日：2018-04-12

申请号：US15831076

申请日：2017-12-04

Applicant: Micron Technology, Inc.

Inventor： Scott James Derner ,  Christopher John Kawamura ,  Charles L. Ingalls

IPC: G11C11/22

Abstract: Methods, systems, and apparatuses related to a reprogrammable non-volatile latch are described. A latch may include ferroelectric cells, ferroelectric capacitors, a sense component, and other circuitry and components related to ferroelectric memory technology. The ferroelectric latch may be independent from (or exclusive of) a main ferroelectric memory array. The ferroelectric latch may be positioned anywhere in the memory device. In some instances, a ferroelectric latch may be positioned and configured to be dedicated to single piece of circuitry in the memory device.