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公开(公告)号：US20240290373A1
公开(公告)日：2024-08-29
申请号：US18598888
申请日：2024-03-07
Applicant: Micron Technology, Inc.
Inventor： Martin Brox , C. Omar Benitez , Johnathan L. Gossi , Christopher John Kawamura
IPC: G11C11/408 , G11C5/14 , G11C11/22 , G11C11/4094
CPC classification number: G11C11/4085 , G11C5/14 , G11C11/2259 , G11C11/4094 , G11C11/221
Abstract: Methods, systems, and devices for techniques for generating access line voltages are described. A system may use a first voltage supply and a second voltage supply that is configured to supply a lower voltage than the first voltage supply. The system may activate a first circuit to couple a node with the first voltage supply so that a first voltage develops on the node from the first voltage supply. The system may activate a second circuit to couple the node with the second voltage supply so that a second voltage that is lower than the first voltage develops on the node from the second voltage supply.
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公开(公告)号：US11948622B2
公开(公告)日：2024-04-02
申请号：US17659405
申请日：2022-04-15
Applicant: Micron Technology, Inc.
Inventor： Martin Brox , C. Omar Benitez , Johnathan L. Gossi , Christopher John Kawamura
IPC: G11C11/40 , G11C5/14 , G11C11/22 , G11C11/408 , G11C11/4094
CPC classification number: G11C11/4085 , G11C5/14 , G11C11/2259 , G11C11/4094 , G11C11/221
Abstract: Methods, systems, and devices for techniques for generating access line voltages are described. A system may use a first voltage supply and a second voltage supply that is configured to supply a lower voltage than the first voltage supply. The system may activate a first circuit to couple a node with the first voltage supply so that a first voltage develops on the node from the first voltage supply. The system may activate a second circuit to couple the node with the second voltage supply so that a second voltage that is lower than the first voltage develops on the node from the second voltage supply.
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公开(公告)号：US11646751B2
公开(公告)日：2023-05-09
申请号：US17348654
申请日：2021-06-15
Applicant: Micron Technology, Inc.
Inventor： Markus H. Geiger , Matthew A. Prather , Sujeet Ayyapureddi , C. Omar Benitez , Dennis Montierth
CPC classification number: H03M13/095 , G06F11/1076
Abstract: Apparatuses, systems, and methods for multi-bit error detection. A memory device may store data bits and parity bits in a memory array. An error correction code (ECC) circuit may generate syndrome bits based on the data and parity bits and use the syndrome bits to correct up to a single bit error in the data and parity bits. A multi-bit error (MBE) detection circuit may detect an MBE in the data and parity based on at least one of the syndrome bits or the parity bits. For example, the MBE detection circuit may determine if the syndrome bits have a mapped or unmapped state and/or may compare the parity bits, data bits, and an additional parity bit to determine if there is an MBE. When an MBE is detected an MBE signal is activated. In some embodiments, an MBE flag may be set based on the MBE signal being active.
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公开(公告)号：US20230335179A1
公开(公告)日：2023-10-19
申请号：US17659405
申请日：2022-04-15
Applicant: Micron Technology, Inc.
Inventor： Martin Brox , C. Omar Benitez , Johnathan L. Gossi , Christopher John Kawamura
IPC: G11C11/408 , G11C11/4094 , G11C11/22
CPC classification number: G11C11/4085 , G11C11/4094 , G11C11/2259 , G11C11/221
Abstract: Methods, systems, and devices for techniques for generating access line voltages are described. A system may use a first voltage supply and a second voltage supply that is configured to supply a lower voltage than the first voltage supply. The system may activate a first circuit to couple a node with the first voltage supply so that a first voltage develops on the node from the first voltage supply. The system may activate a second circuit to couple the node with the second voltage supply so that a second voltage that is lower than the first voltage develops on the node from the second voltage supply.
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Patent Agency Ranking
公开(公告)号：US20220399902A1
公开(公告)日：2022-12-15
申请号：US17348654
申请日：2021-06-15
Applicant: Micron Technology, Inc.
Inventor： Markus H. Geiger , Matthew A. Prather , Sujeet Ayyapureddi , C. Omar Benitez , Dennis Montierth
Abstract: Apparatuses, systems, and methods for multi-bit error detection. A memory device may store data bits and parity bits in a memory array. An error correction code (ECC) circuit may generate syndrome bits based on the data and parity bits and use the syndrome bits to correct up to a single bit error in the data and parity bits. A multi-bit error (MBE) detection circuit may detect an MBE in the data and parity based on at least one of the syndrome bits or the parity bits. For example, the MBE detection circuit may determine if the syndrome bits have a mapped or unmapped state and/or may compare the parity bits, data bits, and an additional parity bit to determine if there is an MBE. When an MBE is detected an MBE signal is activated. In some embodiments, an MBE flag may be set based on the MBE signal being active.
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公开(公告)号：US20200243155A1
公开(公告)日：2020-07-30
申请号：US16852239
申请日：2020-04-17
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Christian N. Mohr , Gregg D. Wolff , Christopher G. Wieduwilt , C. Omar Benitez , Dennis G. Montierth
Abstract: An apparatus may include a memory array, a test circuit coupled to the memory array, a counter circuit coupled to the test circuit and an input/output (I/O) circuit coupled to the counter circuit. During a test operation, the test circuit may receive blocks of data from the memory array and compare the data to detect errors in the blocks of data. The counter circuit may increment a count value in response to detection of an error by the test circuit, and the I/O circuit may provide the count value to an output. The test circuit may also provide test comparison data based on the received blocks of data, and the I/O circuit may provide one of the count value and the test comparison data to the output.
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公开(公告)号：US11437116B2
公开(公告)日：2022-09-06
申请号：US16852239
申请日：2020-04-17
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Christian N. Mohr , Gregg D. Wolff , Christopher G. Wieduwilt , C. Omar Benitez , Dennis G. Montierth
Abstract: An apparatus may include a memory array, a test circuit coupled to the memory array, a counter circuit coupled to the test circuit and an input/output (I/O) circuit coupled to the counter circuit. During a test operation, the test circuit may receive blocks of data from the memory array and compare the data to detect errors in the blocks of data. The counter circuit may increment a count value in response to detection of an error by the test circuit, and the I/O circuit may provide the count value to an output. The test circuit may also provide test comparison data based on the received blocks of data, and the I/O circuit may provide one of the count value and the test comparison data to the output.
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公开(公告)号：US10930327B1
公开(公告)日：2021-02-23
申请号：US16773824
申请日：2020-01-27
Applicant: Micron Technology, Inc.
Inventor： Dave Jefferson , C. Omar Benitez , Yoshinori Fujiwara , Christopher S. Wieduwilt , Vivek Kotti , Dennis G. Montierth , Joshua E. Alzheimer , Daniel S. Miller , Kevin G. Werhane , Jason M. Johnson
Abstract: Methods, systems, and devices for memory read masking are described. In some cases, a portion of a memory device, such as a portion of a memory array, may be disabled. During a testing operation, a command for accessing one or more memory cells of the disabled portion may be received, and the associated memory cells may be attempted to be accessed. Based on attempting to access the disabled memory cells, a logic state of the disabled cells may be masked. Outputting the masked value may indicate (e.g., to a testing device) that the disabled cells pass the test (e.g., that the memory cells are valid), which may allow for the enabled memory cells and the disabled memory cells of the memory device to be tested using a single test mode.
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公开(公告)号：US20200005885A1
公开(公告)日：2020-01-02
申请号：US16020806
申请日：2018-06-27
Applicant: Micron Technology, Inc.
Inventor： Christian N. Mohr , Gregg D. Wolff , Christopher G. Wieduwilt , C. Omar Benitez , Dennis G. Montierth
Abstract: An apparatus may include a memory array, a test circuit coupled to the memory array, a counter circuit coupled to the test circuit and an input/output (I/O) circuit coupled to the counter circuit. During a test operation, the test circuit may receive blocks of data from the memory array and compare the data to detect errors in the blocks of data. The counter circuit may increment a count value in response to detection of an error by the test circuit, and the I/O circuit may provide the count value to an output. The test circuit may also provide test comparison data based on the received blocks of data, and the I/O circuit may provide one of the count value and the test comparison data to the output.
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