Side-channel protection
    1.
    发明授权

    公开(公告)号:US11308203B2

    公开(公告)日:2022-04-19

    申请号:US16246434

    申请日:2019-01-11

    Abstract: In various examples there is a computing device in communication with at least one other computing device via a communications network. The computing device has a memory and a central processing unit having a trusted execution environment comprising trusted regions of the memory. The computing device has an operating system configured to create a memory mapping between a virtual address space of the memory and a memory of the at least one other computing device and to provide details of the memory mapping to the trusted execution environment. The trusted execution environment is configured to execute an application which is able to communicate with the other computing device directly using the memory mapping provided by the operating system.

    Side-channel protection
    2.
    发明授权

    公开(公告)号:US11995179B2

    公开(公告)日:2024-05-28

    申请号:US17713247

    申请日:2022-04-05

    Abstract: In various examples there is a computing device in communication with at least one other computing device via a communications network. The computing device has a memory and a central processing unit having a trusted execution environment comprising trusted regions of the memory. The computing device has an operating system configured to create a memory mapping between a virtual address space of the memory and a memory of the at least one other computing device and to provide details of the memory mapping to the trusted execution environment. The trusted execution environment is configured to execute an application which is able to communicate with the other computing device directly using the memory mapping provided by the operating system.

    Compute node security
    3.
    发明授权

    公开(公告)号:US10565129B2

    公开(公告)日:2020-02-18

    申请号:US15637685

    申请日:2017-06-29

    Abstract: In various examples a compute node is described. The compute node has a central processing unit which implements a hardware transactional memory using at least one cache of the central processing unit. The compute node has a memory in communication with the central processing unit, the memory storing information comprising at least one of: code and data. The compute node has a processor which loads at least part of the information, from the memory into the cache. The processor executes transactions using the hardware transactional memory and at least the loaded information, such that the processor ensures that the loaded information remains in the cache until completion of the execution.

Patent Agency Ranking