公开(公告)号：US20210119125A1

公开(公告)日：2021-04-22

申请号：US17135632

申请日：2020-12-28

Applicant: Microsoft Technology Licensing, LLC

Inventor： Peter Krogstrup Jeppesen ,  Yu Liu ,  Alessandra Luchini

IPC: H01L49/00 ,  H01L29/06 ,  H01L39/00 ,  H01L43/10 ,  H01L29/20

Abstract: A first aspect provides a topological quantum computing device comprising a network of semiconductor-superconductor nanowires, each nanowire comprising a length of semiconductor formed over a substrate and a coating of superconductor formed over at least part of the semiconductor; wherein at least some of the nanowires further comprise a coating of ferromagnetic insulator disposed over at least part of the semiconductor. A second aspect provides a method of fabricating a quantum or spintronic device comprising a heterostructure of semiconductor and ferromagnetic insulator, by: forming a portion of the semiconductor over a substrate in a first vacuum chamber, and growing a coating of the ferromagnetic insulator on the semiconductor by epitaxy in a second vacuum chamber connected to the first vacuum chamber by a vacuum tunnel, wherein the semiconductor comprises InAs and the ferromagnetic insulator comprises EuS.

公开(公告)号：US10692010B2

公开(公告)日：2020-06-23

申请号：US16120433

申请日：2018-09-03

Applicant: Microsoft Technology Licensing, LLC

Inventor： Michael Hartley Freedman ,  Bernard van Heck ,  Georg Wolfgang Winkler ,  Torsten Karzig ,  Roman Lutchyn ,  Peter Krogstrup Jeppesen ,  Chetan Nayak ,  Charles Masamed Marcus ,  Saulius Vaitiekenas

IPC: H01L39/22 ,  G06N10/00 ,  H01L27/18 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66 ,  H01L39/12 ,  H01L39/24 ,  B82Y10/00

Abstract: The disclosure relates to a quantum device and method of fabricating the same. The device comprises one or more semiconductor-superconductor nanowires, each comprising a length of semiconductor material and a coating of superconductor material coated on the semiconductor material. The nanowires may be formed over a substrate. In a first aspect at least some of the nanowires are full-shell nanowires with superconductor material being coated around a full perimeter of the semiconductor material along some or all of the length of the wire, wherein the device is operable to induce at least one Majorana zero mode, MZM, in one or more active ones of the full-shell nanowires. In a second aspect at least some of the nanowires are arranged vertically relative to the plane of the substrate in the finished device.

公开(公告)号：US20230422633A1

公开(公告)日：2023-12-28

申请号：US18039202

申请日：2020-12-04

Applicant: Microsoft Technology Licensing, LLC

Inventor： Keita Otani ,  Peter Krogstrup Jeppesen

IPC: H10N60/01 ,  H10N60/12 ,  H10N60/85 ,  H10N60/81

CPC classification number: H10N60/0912 ,  H10N60/12 ,  H10N60/855 ,  H10N60/815

Abstract: A method of forming a thin film of material on a surface of a substrate, the substrate comprising a semiconductor, comprises: depositing a thin film of metal on the surface of the substrate, wherein the deposition is performed in an ultra-high vacuum, and wherein the substrate is at a temperature of less than or equal to 260 K during the deposition. Cooling the substrate during deposition of the thin film of metal may allow for an atomically flat and very uniform thin film to be obtained. Also provided is a device obtainable by the method.

公开(公告)号：US20210083166A1

公开(公告)日：2021-03-18

申请号：US16570745

申请日：2019-09-13

Applicant: Microsoft Technology Licensing, LLC

Inventor： Dmitry Igorevich Pikulin ,  Geoffrey Charles Gardner ,  Raymond Leonard Kallaher ,  Georg Wolfgang Winkler ,  Sergei Vyatcheslavovich Gronin ,  Peter Krogstrup Jeppesen ,  Michael James Manfra ,  Andrey Antipov ,  Roman Mykolayovych Lutchyn

IPC: H01L39/02 ,  H01L27/18 ,  H01L39/12 ,  H01L39/22 ,  H01L39/24 ,  G06N10/00

Abstract: A device comprising: a portion of semiconductor; a portion of superconductor arranged to a enable a topological phase having a topological gap to be induced in a region of the semiconductor by proximity effect; and a portion of a non-magnetic material comprising an element with atomic number Z greater than or equal to 26, arranged to increase the topological gap in the topological region of the semiconductor.

公开(公告)号：US12171148B2

公开(公告)日：2024-12-17

申请号：US17382174

申请日：2021-07-21

Applicant: Microsoft Technology Licensing, LLC

Inventor： Kevin Van Hoogdalem ,  Leonardus Kouwenhoven ,  Pavel Aseev ,  Peter Krogstrup Jeppesen

IPC: H10N69/00 ,  C23C14/28 ,  C30B11/12 ,  C30B23/06 ,  H01L29/06 ,  H10N60/01 ,  H10N60/10 ,  H10N60/82 ,  B82Y10/00 ,  G06N10/00

Abstract: Various fabrication methods are disclosed. In one such method, at least one structure is formed on a substrate which protrudes outwardly from a plane of the substrate. A beam is used to form a layer of material, at least part of which is in direct contact with a semiconductor structure on the substrate, the semiconductor structure comprising at least one nanowire. The beam has a non-zero angle of incidence relative to the normal of the plane of the substrate such that the beam is incident on one side of the protruding structure, thereby preventing a portion of the nanowire in a shadow region adjacent the other side of the protruding structure in the plane of the substrate from being covered with the material.

公开(公告)号：US20230247918A1

公开(公告)日：2023-08-03

申请号：US18054488

申请日：2022-11-10

Applicant: Microsoft Technology Licensing, LLC

Inventor： Peter Krogstrup Jeppesen

IPC: H10N69/00 ,  C23C14/28 ,  C30B11/12 ,  C30B23/06 ,  H01L29/06 ,  H10N60/01 ,  H10N60/10 ,  H10N60/82

CPC classification number: H10N69/00 ,  C23C14/28 ,  C30B11/12 ,  C30B23/06 ,  H01L29/0669 ,  H10N60/0884 ,  H10N60/01 ,  H10N60/10 ,  H10N60/82 ,  H10N60/0801 ,  B82Y10/00

Abstract: A mixed semiconductor-superconductor platform is fabricated in phases. In a masking phase, a dielectric mask is formed on a substrate, such that the dielectric mask leaves one or more regions of the substrate exposed. In a selective area growth phase, a semiconductor material is selectively grown on the substrate in the one or more exposed regions. In a superconductor growth phase, a layer of superconducting material is formed, at least part of which is in direct contact with the selectively grown semiconductor material. The mixed semiconductor-superconductor platform comprises the selectively grown semiconductor material and the superconducting material in direct contact with the selectively grown semiconductor material.

公开(公告)号：US20220102425A1

公开(公告)日：2022-03-31

申请号：US17382174

申请日：2021-07-21

Applicant: Microsoft Technology Licensing, LLC

Inventor： Kevin Van Hoogdalem ,  Leonardus Kouwenhoven ,  Pavel Aseev ,  Peter Krogstrup Jeppesen

IPC: H01L27/18 ,  C23C14/28 ,  C30B11/12 ,  C30B23/06 ,  H01L29/06 ,  H01L39/22 ,  H01L39/24 ,  H01L39/06

Abstract: Various fabrication methods are disclosed. In one such method, at least one structure is formed on a substrate which protrudes outwardly from a plane of the substrate. A beam is used to form a layer of material, at least part of which is in direct contact with a semiconductor structure on the substrate, the semiconductor structure comprising at least one nanowire. The beam has a non-zero angle of incidence relative to the normal of the plane of the substrate such that the beam is incident on one side of the protruding structure, thereby preventing a portion of the nanowire in a shadow region adjacent the other side of the protruding structure in the plane of the substrate from being covered with the material.

公开(公告)号：US11974509B2

公开(公告)日：2024-04-30

申请号：US18054488

申请日：2022-11-10

Applicant: Microsoft Technology Licensing, LLC

Inventor： Peter Krogstrup Jeppesen

IPC: H10N69/00 ,  B82Y10/00 ,  C23C14/28 ,  C30B11/12 ,  C30B23/06 ,  G06N10/00 ,  H01L29/06 ,  H10N60/01 ,  H10N60/10 ,  H10N60/82

CPC classification number: H10N69/00 ,  C23C14/28 ,  C30B11/12 ,  C30B23/06 ,  H01L29/0669 ,  H10N60/01 ,  H10N60/0801 ,  H10N60/0884 ,  H10N60/10 ,  H10N60/82 ,  B82Y10/00 ,  G06N10/00

Abstract: A mixed semiconductor-superconductor platform is fabricated in phases. In a masking phase, a dielectric mask is formed on a substrate, such that the dielectric mask leaves one or more regions of the substrate exposed. In a selective area growth phase, a semiconductor material is selectively grown on the substrate in the one or more exposed regions. In a superconductor growth phase, a layer of superconducting material is formed, at least part of which is in direct contact with the selectively grown semiconductor material. The mixed semiconductor-superconductor platform comprises the selectively grown semiconductor material and the superconducting material in direct contact with the selectively grown semiconductor material.

公开(公告)号：US20220260915A1

公开(公告)日：2022-08-18

申请号：US17597838

申请日：2019-07-29

Applicant: Microsoft Technology Licensing, LLC

Inventor： Peter Krogstrup Jeppesen ,  Pasi Kostamo ,  Tomas Stankevic

IPC: G03F7/12 ,  C23C16/04

Abstract: A method for collimating a beam of material being deposited on a substrate at a deposition area of the substrate is disclosed. The substrate is masked with a stencil mask located at a mask distance from the substrate, the mask distance being the distance between a top face of the substrate and an outer face of the mask facing the substrate. The beam is projected from a source cell located at a source distance from the mask, the source distance being the distance between the source cell and an outer face of the mask facing the source cell. The stencil mask comprises two mask layers separated by a layer separation distance which is great than zero. Each mask layer comprises a slit, the slits of the two layers having a width being aligned in a plane of the substrate.

公开(公告)号：US11296145B2

公开(公告)日：2022-04-05

申请号：US16484088

申请日：2018-10-26

Applicant: Microsoft Technology Licensing, LLC

Inventor： Kevin Van Hoogdalem ,  Leonardus Kouwenhoven ,  Pavel Aseev ,  Peter Krogstrup Jeppesen

IPC: H01L27/18 ,  C23C14/28 ,  C30B11/12 ,  C30B23/06 ,  H01L29/06 ,  H01L39/22 ,  H01L39/24 ,  H01L39/06 ,  G06N10/00 ,  B82Y10/00

Abstract: Various fabrication method are disclosed. In one such method, at least one structure is formed on a substrate which protrudes outwardly from a plane of the substrate. A beam is used to form a layer of material, at least part of which is in direct contact with a semiconductor structure on the substrate, the semiconductor structure comprising at least one nanowire. The beam has a non-zero angle of incidence relative to the normal of the plane of the substrate such that the beam is incident on one side of the protruding structure, thereby preventing a portion of the nanowire in a shadow region adjacent the other side of the protruding structure in the plane of the substrate from being covered with the material.