公开(公告)号：US20220164118A1

公开(公告)日：2022-05-26

申请号：US17102084

申请日：2020-11-23

Applicant: Microsoft Technology Licensing, LLC

Inventor： Lisa Ru-Feng HSU ,  Aninda MANOCHA ,  Ishwar AGARWAL ,  Daniel Sebastian BERGER ,  Stanko NOVAKOVIC ,  Janaina Barreiro GAMBARO BUENO ,  Vishal SONI

IPC: G06F3/06

Abstract: The present disclosure relates to systems, methods, and computer-readable media for managing tracked memory usage data and performing various actions based on memory usage data tracked by a memory controller on a memory device. For example, systems described herein involve collecting and compiling data across one or more memory controllers to evaluate characteristics of the memory usage data to determine hotness metric(s) for segments of a memory resource. The systems described herein may perform a variety of segment actions based on the hotness metric(s). In addition, the systems described herein can compile the memory usage data according to one or more access granularities. This compiled data may further be shared with multiple accessing agents in accordance with access resolutions of the respective accessing agents.

公开(公告)号：US20240235806A9

公开(公告)日：2024-07-11

申请号：US17973471

申请日：2022-10-25

Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC

Inventor： Bharat S. PILLILLI ,  Bryan David KELLY ,  Vishal SONI

IPC: H04L9/00 ,  G01R31/3181 ,  H04L9/08

CPC classification number: H04L9/002 ,  G01R31/3181 ,  H04L9/0894

Abstract: The techniques disclosed herein are directed to devices, circuits, systems, and techniques to mitigate the impact of side-channel attacks on a cryptography function in a target system. The Razor flip-flops are inserted into critical paths of the cryptography function of the target system, including at rest blocks such as key vaults and data vaults, and also including registers and/or pipelines used for calculations within the cryptography functions. Errors detected by the Razor flip-flops are processed by error detection logic in the cryptographic function, which continues the calculations until completion. The generated key and data value pairs resulting from detected errors are discarded, silently ignored without disrupting the calculation process. The schemes disclosed herein mitigate the impact of side-channel attacks with a digital logic based implementation, with reduced complexity and reduced cost.

公开(公告)号：US20240137203A1

公开(公告)日：2024-04-25

申请号：US17973471

申请日：2022-10-24

Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC

Inventor： Bharat S. PILLILLI ,  Bryan David KELLY ,  Vishal SONI

IPC: H04L9/00 ,  G01R31/3181 ,  H04L9/08

CPC classification number: H04L9/002 ,  G01R31/3181 ,  H04L9/0894

Abstract: The techniques disclosed herein are directed to devices, circuits, systems, and techniques to mitigate the impact of side-channel attacks on a cryptography function in a target system. The Razor flip-flops are inserted into critical paths of the cryptography function of the target system, including at rest blocks such as key vaults and data vaults, and also including registers and/or pipelines used for calculations within the cryptography functions. Errors detected by the Razor flip-flops are processed by error detection logic in the cryptographic function, which continues the calculations until completion. The generated key and data value pairs resulting from detected errors are discarded, silently ignored without disrupting the calculation process. The schemes disclosed herein mitigate the impact of side-channel attacks with a digital logic based implementation, with reduced complexity and reduced cost.

公开(公告)号：US20220066827A1

公开(公告)日：2022-03-03

申请号：US17011805

申请日：2020-09-03

Applicant: Microsoft Technology Licensing, LLC

Inventor： Siamak TAVALLAEI ,  Vishal SONI ,  Ishwar AGARWAL

IPC: G06F9/50 ,  G06F9/30 ,  G06F9/46 ,  G06F9/4401 ,  G06F12/02

Abstract: Examples are disclosed that relate to a disaggregated memory pool. One example provides a memory system comprising a memory controller and memory attached to the memory controller and forming at least a portion of a disaggregated memory pool, the disaggregated memory pool including a plurality of slices that are each dynamically assigned to a respective compute node. The memory system is configured to receive a request to adjust an assignment of the memory pool to a requesting compute node, where the portion of the memory pool includes an unassigned slice that can satisfy the request, assign at least part of the unassigned portion to the requesting compute node, and where the portion of the memory pool does not include an unassigned slice that can satisfy the request, cause a request to be directed to another compute node to free at least one slice to the such compute node.

公开(公告)号：US20240361947A1

公开(公告)日：2024-10-31

申请号：US18766119

申请日：2024-07-08

Applicant: Microsoft Technology Licensing, LLC

Inventor： Lisa Ru-Feng HSU ,  Aninda MANOCHA ,  Ishwar AGARWAL ,  Daniel Sebastian BERGER ,  Stanko NOVAKOVIC ,  Janaina Barreiro GAMBARO BUENO ,  Vishal SONI

IPC: G06F3/06

CPC classification number: G06F3/0653 ,  G06F3/0608 ,  G06F3/0673

Abstract: The present disclosure relates to systems, methods, and computer-readable media for tracking memory usage data on a memory controller system and providing a mechanism whereby one or multiple accessing agents (e.g., computing nodes, applications, virtual machines) can access memory usage data for a memory resource managed by a memory controller. Indeed, the systems described herein facilitate generation of and access to heatmaps having memory usage data thereon. The systems described herein describe features and functionality related to generating and maintaining the heatmaps as well as providing access to the heatmaps to a variety of accessing agents. This memory tracking and accessing is performed using low processing overhead while providing useful information to accessing agents in connection with memory resources managed by a memory controller.

公开(公告)号：US20230315626A1

公开(公告)日：2023-10-05

申请号：US18024590

申请日：2021-05-31

Applicant: Microsoft Technology Licensing, LLC

Inventor： Siamak TAVALLAEI ,  Ishwar AGARWAL ,  Vishal SONI

IPC: G06F12/06 ,  G06F9/50

CPC classification number: G06F12/0653 ,  G06F12/0607 ,  G06F9/5016

Abstract: A method for memory address mapping in a disaggregated memory system includes receiving an indication of one or more ranges of host physical addresses (HPAs) from a compute node of a plurality of compute nodes, the one or more ranges of HPAs including a plurality of memory addresses corresponding to different allocation slices of the disaggregated memory pool that are allocated to the compute node. The one or more ranges of HPAs are converted into a contiguous range of device physical addresses (DPAs). For each DPA, a target address decoder (TAD) is identified based on a slice identifier and a slice-to-TAD index. Each DPA is mapped to a media-specific physical element of a physical memory unit of the disaggregated memory pool based on the TAD.

公开(公告)号：US20220382873A1

公开(公告)日：2022-12-01

申请号：US17335980

申请日：2021-06-01

Applicant: Microsoft Technology Licensing, LLC

Inventor： Vishal SONI ,  Bryan David KELLY

IPC: G06F21/57 ,  H04L9/30 ,  H04L9/32

Abstract: A system includes a stored counter value and a stored boot manifest including a manifest type flag. A manifest type of the boot manifest is determined based on the manifest type flag, a tenancy mode is determined based on a parity of the counter value, a first boot is executed if the manifest type is a first manifest type and the tenancy mode is a first tenancy mode, a second boot flow is executed if the manifest type is the first manifest type and the tenancy mode is a second tenancy mode, a third boot flow is executed if the manifest type is a second manifest type and the tenancy mode is the first tenancy mode, and a fourth boot flow is executed if the manifest type is the second manifest type and the tenancy mode is the second tenancy mode.

公开(公告)号：US20230385410A1

公开(公告)日：2023-11-30

申请号：US17838446

申请日：2022-06-13

Applicant: Microsoft Technology Licensing, LLC

Inventor： Ishwar AGARWAL ,  Bharat PILLILLI ,  Vishal SONI

IPC: G06F21/55 ,  G06F21/54 ,  G06F21/79 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F21/556 ,  G06F21/54 ,  G06F21/552 ,  G06F21/79 ,  G06F9/30047 ,  G06F9/3857

Abstract: Systems and methods related to flush plus reload cache side-channel attack mitigation are described. An example method for mitigating a side-channel timing attack in a system including a processor having at least one cache is described. The method includes receiving a first instruction, where the first instruction, when executed by the processor, is configured to flush at least one cache line from the at least one cache associated with the processor. The method further includes, prior to execution of the first instruction by the processor, automatically mapping the first instruction to a second instruction such that the at least one cache line is not flushed from the at least one cache even in response to receiving the first instruction.

公开(公告)号：US20230325225A1

公开(公告)日：2023-10-12

申请号：US17716823

申请日：2022-04-08

Applicant: Microsoft Technology Licensing, LLC

Inventor： Ishwar AGARWAL ,  Bryan David KELLY ,  Vishal SONI

IPC: G06F9/455

CPC classification number: G06F9/45558 ,  G06F2009/45583 ,  G06F2009/4557 ,  G06F2009/45579

Abstract: Systems and methods for a confidential compute architecture integrated with direct swap caching are described. An example method for managing a near memory and a far memory includes, in response to determining that the far memory contains an encrypted version of a first block of data, retrieving from the far memory the encrypted version of the first block of data, decrypting the first block of data using a first key for exclusive use by a first virtual machine associated with the system, and providing a decrypted version of the first block of data to the requestor. The method further includes swapping out a second block of data having an address conflict with the first block of data from the near memory to the far memory, where the second block of data is encrypted using a second key for exclusive use by a second virtual machine associated with the system.

公开(公告)号：US20220121386A1

公开(公告)日：2022-04-21

申请号：US17071344

申请日：2020-10-15

Applicant: Microsoft Technology Licensing, LLC

Inventor： Lisa Ru-Feng HSU ,  Aninda MANOCHA ,  Ishwar AGARWAL ,  Daniel Sebastian BERGER ,  Stanko NOVAKOVIC ,  Janaina Barreiro GAMBARO BUENO ,  Vishal SONI

IPC: G06F3/06

Abstract: The present disclosure relates to systems, methods, and computer-readable media for tracking memory usage data on a memory controller system and providing a mechanism whereby one or multiple accessing agents (e.g., computing nodes, applications, virtual machines) can access memory usage data for a memory resource managed by a memory controller. Indeed, the systems described herein facilitate generation of and access to heatmaps having memory usage data thereon. The systems described herein describe features and functionality related to generating and maintaining the heatmaps as well as providing access to the heatmaps to a variety of accessing agents. This memory tracking and accessing is performed using low processing overhead while providing useful information to accessing agents in connection with memory resources managed by a memory controller.