公开(公告)号：US08753956B2

公开(公告)日：2014-06-17

申请号：US13724284

申请日：2012-12-21

申请人： Mieno Fumitake ,  Meisheng Zhou

发明人： Mieno Fumitake ,  Meisheng Zhou

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L29/06

CPC分类号： H01L21/76229 ,  H01L21/76232 ,  H01L21/823431 ,  H01L29/0649

摘要： A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having a first region and an adjacent second region, and etching the semiconductor substrate to form a plurality of first trenches in the first region and a second trench in the second region. Fins are formed in between the adjacent first trenches. The width of the second trench is greater than the width of the first trench. The method also includes filling the first trenches with a first isolation material to form first insolation structures, and form sidewall spacers inside the second trench. Further, the method includes forming a third trench in the second trench by etching the exposed semiconductor substrate on the bottom of the second trench using the sidewall spacers as an etching mask, and filling the second trench and the third trench using a second isolation material to form a second isolation structure.

摘要翻译： 提供了制造半导体结构的方法。 该方法包括提供具有第一区域和相邻第二区域的半导体衬底，并且蚀刻半导体衬底以在第一区域中形成多个第一沟槽和在第二区域中形成第二沟槽。 鳍形成在相邻的第一沟槽之间。 第二沟槽的宽度大于第一沟槽的宽度。 该方法还包括用第一隔离材料填充第一沟槽以形成第一日照结构，并在第二沟槽内形成侧壁间隔物。 此外，该方法包括通过使用侧壁间隔物作为蚀刻掩模蚀刻在第二沟槽的底部上的暴露的半导体衬底，在第二沟槽中形成第三沟槽，并且使用第二隔离材料填充第二沟槽和第三沟槽 形成第二隔离结构。

公开(公告)号：US08912102B2

公开(公告)日：2014-12-16

申请号：US12396441

申请日：2009-03-02

申请人： Chyiu Hyia Poon ,  Alex K H See ,  Meisheng Zhou

发明人： Chyiu Hyia Poon ,  Alex K H See ,  Meisheng Zhou

IPC分类号： H01L21/00 ,  H01L21/268 ,  H01L21/324

CPC分类号： H01L21/268 ,  H01L21/324

摘要： A system for and method of processing an article such as a semiconductor wafer is disclosed. The wafer includes first and second surfaces which are segmented into a plurality of first and second zones. The first surface of the wafer, for example, on which devices or ICs are formed is processed by, for example, laser annealing while the second surface is heated with a backside heating source. Corresponding, or at least substantially corresponding, zones on the first and second surfaces are processed synchronously to reduce variations of post laser anneal thermal budget across the wafer.

摘要翻译： 公开了一种用于处理诸如半导体晶片的物品的系统和方法。 晶片包括被分段成多个第一和第二区域的第一和第二表面。 例如通过激光退火处理例如在其上形成有器件或IC的晶片的第一表面，同时用背面加热源加热第二表面。 在第一和第二表面上相应或至少基本对应的区域被同步地处理，以减少晶片上后激光退火热预算的变化。

公开(公告)号：US20110157567A1

公开(公告)日：2011-06-30

申请号：US12649212

申请日：2009-12-29

申请人： Wenzhan Zhou ,  Sia Kim Tan ,  Lei Yuan ,  Meisheng Zhou

发明人： Wenzhan Zhou ,  Sia Kim Tan ,  Lei Yuan ,  Meisheng Zhou

IPC分类号： G03B27/52

CPC分类号： G03F7/70341

摘要： A liquid immersion scanning exposure system utilizes an immersion liquid confined within a watertight lens hood having a base portion formed from a solid optical element. During operation, a bottom portion of a lens assembly is disposed within the immersion liquid and the solid optical element is placed upon a photoresist material or layer (to be patterned). The lens assembly moves laterally through the immersion liquid parallel to the photoresist material. Because the solid optical element separates the immersion liquid from the photoresist material and does not move relative to the photoresist material, the photoresist material does not contact with the immersion liquid and the solid optical element and is not susceptible to damage or scratching by the solid optical element.

摘要翻译： 液浸式扫描曝光系统利用限制在具有由固体光学元件形成的基部的防水透镜罩内的浸液。 在操作期间，透镜组件的底部设置在浸没液体内，并且固体光学元件被放置在光致抗蚀剂材料或层（待图案化）上。 透镜组件横向移动通过平行于光致抗蚀剂材料的浸没液体。 由于固体光学元件将浸没液体与光致抗蚀剂材料分离并且不相对于光致抗蚀剂材料移动，所以光致抗蚀剂材料不与浸没液体和固体光学元件接触，并且不易受固体光学元件的损坏或划伤 元件。

公开(公告)号：US07892900B2

公开(公告)日：2011-02-22

申请号：US12098751

申请日：2008-04-07

申请人： Huang Liu ,  Wei Lu ,  Hai Cong ,  Alex K. H. See ,  Hui Peng Koh ,  Meisheng Zhou

发明人： Huang Liu ,  Wei Lu ,  Hai Cong ,  Alex K. H. See ,  Hui Peng Koh ,  Meisheng Zhou

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

摘要： An integrated circuit system that includes: providing a substrate including a first device and a second device; configuring the first device and the second device to include a first spacer, a first liner made from a first dielectric layer, and a second spacer made from a sacrificial spacer material; forming a second dielectric layer over the integrated circuit system; forming a first device source/drain and a second device source/drain adjacent the second spacer and through the second dielectric layer; removing the second spacer without damaging the substrate; forming a third dielectric layer over the integrated circuit system before annealing; and forming a fourth dielectric layer over the integrated circuit system that promotes stress within the channel of the first device, the second device, or a combination thereof.

摘要翻译： 一种集成电路系统，包括：提供包括第一装置和第二装置的基板; 配置第一器件和第二器件以包括第一间隔物，由第一介电层制成的第一衬垫和由牺牲间隔物材料制成的第二间隔物; 在所述集成电路系统上形成第二电介质层; 形成第一器件源极/漏极和邻近第二间隔物并通过第二介电层的第二器件源极/漏极; 去除所述第二间隔物而不损坏所述基底; 在退火之前在集成电路系统上形成第三电介质层; 以及在所述集成电路系统上形成促进所述第一装置，所述第二装置或其组合的通道内的应力的第四电介质层。

公开(公告)号：US07928020B2

公开(公告)日：2011-04-19

申请号：US11862865

申请日：2007-09-27

申请人： Jinping Liu ,  Ben Ong ,  Zhengquan Zhang ,  Jae Gon Lee ,  Lydia Wong ,  Bin Yang ,  K. H. Alex See ,  Meisheng Zhou ,  Liang Choo Hsia

发明人： Jinping Liu ,  Ben Ong ,  Zhengquan Zhang ,  Jae Gon Lee ,  Lydia Wong ,  Bin Yang ,  K. H. Alex See ,  Meisheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L21/00

CPC分类号： H01L21/3143 ,  H01L21/0214 ,  H01L21/02332 ,  H01L21/28202 ,  H01L21/31155 ,  H01L29/513 ,  H01L29/518

摘要： A method for fabricating a nitrogen-containing dielectric layer and semiconductor device including the dielectric layer in which a silicon oxide layer is formed on a substrate, such that an interface region resides adjacent to substrate and a surface region resides opposite the interface region. Nitrogen is introduced into the silicon oxide layer by applying a nitrogen plasma. After applying nitrogen plasma, the silicon oxide layer is annealed. The processes of introducing nitrogen into the silicon oxide layer and annealing the silicon oxide layer are repeated to create a bi-modal nitrogen concentration profile in the silicon oxide layer. In the silicon oxide layer, the peak nitrogen concentrations are situated away from the interface region and at least one of the peak nitrogen concentrations is situated in proximity to the surface region. A method for fabricating a semiconductor device is incorporating the nitrogen-containing silicon oxide layers also disclosed.

摘要翻译： 一种含氮介电层的制造方法和包括在基板上形成氧化硅层的电介质层的半导体器件，使得界面区域与基板相邻，表面区域与界面区域相对。 通过施加氮等离子体将氮引入到氧化硅层中。 在施加氮等离子体之后，将氧化硅层退火。 重复将氧气引入氧化硅层并退火氧化硅层的过程，以在氧化硅层中产生双峰氮浓度分布。 在氧化硅层中，峰值氮浓度远离界面区域，并且峰值氮浓度中的至少一个位于表面区域附近。 还公开了一种制造半导体器件的方法，其中还包括含氮氧化硅层。

公开(公告)号：US20090250762A1

公开(公告)日：2009-10-08

申请号：US12098751

申请日：2008-04-07

申请人： Huang Liu ,  Wei Lu ,  Hai Cong ,  Alex K.H. See ,  Hui Peng Koh ,  Meisheng Zhou

发明人： Huang Liu ,  Wei Lu ,  Hai Cong ,  Alex K.H. See ,  Hui Peng Koh ,  Meisheng Zhou

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

摘要： An integrated circuit system that includes: providing a substrate including a first device and a second device; configuring the first device and the second device to include a first spacer, a first liner made from a first dielectric layer, and a second spacer made from a sacrificial spacer material; forming a second dielectric layer over the integrated circuit system; forming a first device source/drain and a second device source/drain adjacent the second spacer and through the second dielectric layer; removing the second spacer without damaging the substrate; forming a third dielectric layer over the integrated circuit system before annealing; and forming a fourth dielectric layer over the integrated circuit system that promotes stress within the channel of the first device, the second device, or a combination thereof.

摘要翻译： 一种集成电路系统，包括：提供包括第一装置和第二装置的基板; 配置第一器件和第二器件以包括第一间隔物，由第一介电层制成的第一衬垫和由牺牲间隔物材料制成的第二间隔物; 在所述集成电路系统上形成第二电介质层; 形成第一器件源极/漏极和邻近第二间隔物并通过第二介电层的第二器件源极/漏极; 去除所述第二间隔物而不损坏所述基底; 在退火之前在集成电路系统上形成第三电介质层; 以及在所述集成电路系统上形成促进所述第一装置，所述第二装置或其组合的通道内的应力的第四电介质层。

公开(公告)号：US20070066047A1

公开(公告)日：2007-03-22

申请号：US11162647

申请日：2005-09-18

申请人： Jianhui Ye ,  Kai Hung Alex See ,  Tien-Cheng Lan ,  Meisheng Zhou

发明人： Jianhui Ye ,  Kai Hung Alex See ,  Tien-Cheng Lan ,  Meisheng Zhou

IPC分类号： H01L21/4763 ,  H01L21/302

CPC分类号： H01L21/31144 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an opening on a material layer is provided. First, a dielectric layer is formed on the material layer. Then, a metallic hard mask layer and a cap layer are sequentially formed on the dielectric layer. Thereafter, a patterned photoresist layer is formed on the cap layer. The patterned photoresist layer exposes a portion of the surface of the cap layer. After that, a first etching operation is carried out using the patterned photoresist layer as a mask to remove a portion of the cap layer and the metallic hard mask layer until the surface of the dielectric layer is exposed. Then, the photoresist layer is removed. A second etching operation is carried out using the cap layer and the metallic hard mask layer as a mask to remove a portion of the dielectric layer and form an opening.

摘要翻译： 提供了在材料层上形成开口的方法。 首先，在材料层上形成电介质层。 然后，在电介质层上依次形成金属硬掩模层和盖层。 此后，在盖层上形成图案化的光致抗蚀剂层。 图案化的光致抗蚀剂层暴露盖层表面的一部分。 之后，使用图案化的光致抗蚀剂层作为掩模进行第一蚀刻操作，以除去覆盖层和金属硬掩模层的一部分，直到暴露介电层的表面。 然后，除去光致抗蚀剂层。 使用盖层和金属硬掩模层作为掩模进行第二蚀刻操作，以去除电介质层的一部分并形成开口。

公开(公告)号：US08405222B2

公开(公告)日：2013-03-26

申请号：US12825266

申请日：2010-06-28

申请人： Hong Yu ,  Huang Liu ,  Feng Zhao ,  Meisheng Zhou ,  Liang-Choo Hsia

发明人： Hong Yu ,  Huang Liu ,  Feng Zhao ,  Meisheng Zhou ,  Liang-Choo Hsia

IPC分类号： H01L21/00

CPC分类号： H01L21/76898 ,  H01L21/7684

摘要： A method of manufacture of an integrated circuit system includes: forming an etch stop layer over a bulk substrate; forming a buffer layer on the etch stop layer; forming a hard mask on the buffer layer; forming a through silicon via through the etch stop layer with the hard mask detected and the buffer layer removed with a low down force; and forming a passivation layer on the through silicon via and the etch stop layer.

摘要翻译： 集成电路系统的制造方法包括：在体基板上形成蚀刻停止层; 在所述蚀刻停止层上形成缓冲层; 在缓冲层上形成硬掩模; 通过所述蚀刻停止层形成穿透硅通孔，所述硬掩模被检测并且所述缓冲层以低的下压力去除; 以及在穿通硅通孔和蚀刻停止层上形成钝化层。

公开(公告)号：US20100109045A1

公开(公告)日：2010-05-06

申请号：US12262128

申请日：2008-10-30

申请人： Jin Ping Liu ,  Yisuo Li ,  Alex K.H. See ,  Meisheng Zhou ,  Liang-Choo Hsia

发明人： Jin Ping Liu ,  Yisuo Li ,  Alex K.H. See ,  Meisheng Zhou ,  Liang-Choo Hsia

IPC分类号： H01L21/20 ,  H01L29/06

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： An integrated circuit system that includes: providing a substrate including an active device; forming a trench within the substrate adjacent the active device; forming a first layer with a first lattice constant within the trench; and forming a second layer with a second lattice constant over the first layer, the second lattice constant differing from the first lattice constant.

摘要翻译： 一种集成电路系统，包括：提供包括有源器件的衬底; 在邻近有源器件的衬底内形成沟槽; 在所述沟槽内形成具有第一晶格常数的第一层; 以及在所述第一层上形成具有第二晶格常数的第二层，所述第二晶格常数不同于所述第一晶格常数。

公开(公告)号：US20090088002A1

公开(公告)日：2009-04-02

申请号：US11862865

申请日：2007-09-27

申请人： Jinping Liu ,  Ben Ong ,  Zhengquan Zhang ,  Jae Gon Lee ,  Lydia Wong ,  Bin Yang ,  K. H. See ,  Meisheng Zhou ,  Liang Choo Hsia

发明人： Jinping Liu ,  Ben Ong ,  Zhengquan Zhang ,  Jae Gon Lee ,  Lydia Wong ,  Bin Yang ,  K. H. See ,  Meisheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L21/31

CPC分类号： H01L21/3143 ,  H01L21/0214 ,  H01L21/02332 ,  H01L21/28202 ,  H01L21/31155 ,  H01L29/513 ,  H01L29/518

摘要： A method for fabricating a nitrogen-containing dielectric layer and semiconductor device including the dielectric layer in which a silicon oxide layer is formed on a substrate, such that an interface region resides adjacent to substrate and a surface region resides opposite the interface region. Nitrogen is introduced into the silicon oxide layer by applying a nitrogen plasma. After applying nitrogen plasma, the silicon oxide layer is annealed. The processes of introducing nitrogen into the silicon oxide layer and annealing the silicon oxide layer are repeated to create a bi-modal nitrogen concentration profile in the silicon oxide layer. In the silicon oxide layer, the peak nitrogen concentrations are situated away from the interface region and at least one of the peak nitrogen concentrations is situated in proximity to the surface region. A method for fabricating a semiconductor device is incorporating the nitrogen-containing silicon oxide layers also disclosed.

摘要翻译： 一种含氮介电层的制造方法和包括在基板上形成氧化硅层的电介质层的半导体器件，使得界面区域与基板相邻，表面区域与界面区域相对。 通过施加氮等离子体将氮引入到氧化硅层中。 在施加氮等离子体之后，将氧化硅层退火。 重复将氧气引入氧化硅层并退火氧化硅层的过程，以在氧化硅层中产生双峰氮浓度分布。 在氧化硅层中，峰值氮浓度远离界面区域，并且峰值氮浓度中的至少一个位于表面区域附近。 还公开了一种制造半导体器件的方法，其中还包括含氮氧化硅层。