公开(公告)号：US20090088002A1

公开(公告)日：2009-04-02

申请号：US11862865

申请日：2007-09-27

申请人： Jinping Liu ,  Ben Ong ,  Zhengquan Zhang ,  Jae Gon Lee ,  Lydia Wong ,  Bin Yang ,  K. H. See ,  Meisheng Zhou ,  Liang Choo Hsia

发明人： Jinping Liu ,  Ben Ong ,  Zhengquan Zhang ,  Jae Gon Lee ,  Lydia Wong ,  Bin Yang ,  K. H. See ,  Meisheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L21/31

CPC分类号： H01L21/3143 ,  H01L21/0214 ,  H01L21/02332 ,  H01L21/28202 ,  H01L21/31155 ,  H01L29/513 ,  H01L29/518

摘要： A method for fabricating a nitrogen-containing dielectric layer and semiconductor device including the dielectric layer in which a silicon oxide layer is formed on a substrate, such that an interface region resides adjacent to substrate and a surface region resides opposite the interface region. Nitrogen is introduced into the silicon oxide layer by applying a nitrogen plasma. After applying nitrogen plasma, the silicon oxide layer is annealed. The processes of introducing nitrogen into the silicon oxide layer and annealing the silicon oxide layer are repeated to create a bi-modal nitrogen concentration profile in the silicon oxide layer. In the silicon oxide layer, the peak nitrogen concentrations are situated away from the interface region and at least one of the peak nitrogen concentrations is situated in proximity to the surface region. A method for fabricating a semiconductor device is incorporating the nitrogen-containing silicon oxide layers also disclosed.

摘要翻译： 一种含氮介电层的制造方法和包括在基板上形成氧化硅层的电介质层的半导体器件，使得界面区域与基板相邻，表面区域与界面区域相对。 通过施加氮等离子体将氮引入到氧化硅层中。 在施加氮等离子体之后，将氧化硅层退火。 重复将氧气引入氧化硅层并退火氧化硅层的过程，以在氧化硅层中产生双峰氮浓度分布。 在氧化硅层中，峰值氮浓度远离界面区域，并且峰值氮浓度中的至少一个位于表面区域附近。 还公开了一种制造半导体器件的方法，其中还包括含氮氧化硅层。

公开(公告)号：US07928020B2

公开(公告)日：2011-04-19

申请号：US11862865

申请日：2007-09-27

申请人： Jinping Liu ,  Ben Ong ,  Zhengquan Zhang ,  Jae Gon Lee ,  Lydia Wong ,  Bin Yang ,  K. H. Alex See ,  Meisheng Zhou ,  Liang Choo Hsia

发明人： Jinping Liu ,  Ben Ong ,  Zhengquan Zhang ,  Jae Gon Lee ,  Lydia Wong ,  Bin Yang ,  K. H. Alex See ,  Meisheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L21/00

CPC分类号： H01L21/3143 ,  H01L21/0214 ,  H01L21/02332 ,  H01L21/28202 ,  H01L21/31155 ,  H01L29/513 ,  H01L29/518

摘要： A method for fabricating a nitrogen-containing dielectric layer and semiconductor device including the dielectric layer in which a silicon oxide layer is formed on a substrate, such that an interface region resides adjacent to substrate and a surface region resides opposite the interface region. Nitrogen is introduced into the silicon oxide layer by applying a nitrogen plasma. After applying nitrogen plasma, the silicon oxide layer is annealed. The processes of introducing nitrogen into the silicon oxide layer and annealing the silicon oxide layer are repeated to create a bi-modal nitrogen concentration profile in the silicon oxide layer. In the silicon oxide layer, the peak nitrogen concentrations are situated away from the interface region and at least one of the peak nitrogen concentrations is situated in proximity to the surface region. A method for fabricating a semiconductor device is incorporating the nitrogen-containing silicon oxide layers also disclosed.

摘要翻译： 一种含氮介电层的制造方法和包括在基板上形成氧化硅层的电介质层的半导体器件，使得界面区域与基板相邻，表面区域与界面区域相对。 通过施加氮等离子体将氮引入到氧化硅层中。 在施加氮等离子体之后，将氧化硅层退火。 重复将氧气引入氧化硅层并退火氧化硅层的过程，以在氧化硅层中产生双峰氮浓度分布。 在氧化硅层中，峰值氮浓度远离界面区域，并且峰值氮浓度中的至少一个位于表面区域附近。 还公开了一种制造半导体器件的方法，其中还包括含氮氧化硅层。

公开(公告)号：US07326609B2

公开(公告)日：2008-02-05

申请号：US10908328

申请日：2005-05-06

申请人： Purakh Raj Verma ,  Liang-Choo Hsia ,  Dong Kyun Sohn ,  Guowei Zhang ,  Chew Hoe Ang ,  Yun Ling Tan ,  Zhao Lun ,  Jae Gon Lee ,  Yung Fu Chong

发明人： Purakh Raj Verma ,  Liang-Choo Hsia ,  Dong Kyun Sohn ,  Guowei Zhang ,  Chew Hoe Ang ,  Yun Ling Tan ,  Zhao Lun ,  Jae Gon Lee ,  Yung Fu Chong

IPC分类号： H01L21/8238

CPC分类号： H01L21/82385 ,  H01L21/823814 ,  H01L21/823857 ,  H01L27/11 ,  H01L29/66545 ,  H01L29/7833

摘要： A method and apparatus for manufacturing a semiconductor device is provides a substrate having a first region and a second region. A sacrificial first gate is formed in the first region. Source/drain are formed in the first region. A second region gate dielectric is formed in the second region. A second region gate is formed on the second region gate dielectric. A second region source/drain is formed in the second region. A sacrificial layer is formed over the sacrificial first gate, the source/drain, the first region, and the second region. The sacrificial first gate is exposed. A gate space is formed by removing the sacrificial first gate. A first region gate dielectric is formed in the gate space. A first region gate is formed on the first region gate dielectric. The sacrificial layer is removed.

摘要翻译： 用于制造半导体器件的方法和设备提供具有第一区域和第二区域的衬底。 牺牲第一栅极形成在第一区域中。 源极/漏极形成在第一区域中。 第二区域栅极电介质形成在第二区域中。 第二区域栅极形成在第二区域栅极电介质上。 在第二区域中形成第二区域源极/漏极。 在牺牲第一栅极，源极/漏极，第一区域和第二区域上形成牺牲层。 牺牲的第一个门被暴露。 通过去除牺牲第一栅极形成栅极空间。 在栅极空间中形成第一区域栅极电介质。 第一区栅极形成在第一区栅极电介质上。 牺牲层被去除。

公开(公告)号：US20080087958A1

公开(公告)日：2008-04-17

申请号：US11951833

申请日：2007-12-06

申请人： Purakh Verma ,  Liang-Choo Hsia ,  Dong Kyun Sohn ,  Guowei Zhang ,  Chew Hoe Ang ,  Yun Ling Tan ,  Zhao Lun ,  Jae Gon Lee ,  Yung Fu Chong

发明人： Purakh Verma ,  Liang-Choo Hsia ,  Dong Kyun Sohn ,  Guowei Zhang ,  Chew Hoe Ang ,  Yun Ling Tan ,  Zhao Lun ,  Jae Gon Lee ,  Yung Fu Chong

IPC分类号： H01L27/088

CPC分类号： H01L21/82385 ,  H01L21/823814 ,  H01L21/823857 ,  H01L27/11 ,  H01L29/66545 ,  H01L29/7833

摘要： A semiconductor device provides a substrate having a first region and a second region. A sacrificial first gate is formed in the first region. Source/drain are formed in the first region. A second region gate dielectric is formed in the second region. A second region gate is formed on the second region gate dielectric. A second region source/drain is formed in the second region. A sacrificial layer is formed over the sacrificial first gate, the source/drain, the first region, and the second region. The sacrificial first gate is exposed. A gate space is formed by removing the sacrificial first gate. A first region gate dielectric is formed in the gate space. A first region gate is formed on the first region gate dielectric. The sacrificial layer is removed.

摘要翻译： 半导体器件提供具有第一区域和第二区域的衬底。 牺牲第一栅极形成在第一区域中。 源极/漏极形成在第一区域中。 第二区域栅极电介质形成在第二区域中。 第二区域栅极形成在第二区域栅极电介质上。 在第二区域中形成第二区域源极/漏极。 在牺牲第一栅极，源极/漏极，第一区域和第二区域上形成牺牲层。 牺牲的第一个门被暴露。 通过去除牺牲第一栅极形成栅极空间。 在栅极空间中形成第一区域栅极电介质。 第一区栅极形成在第一区栅极电介质上。 牺牲层被去除。

公开(公告)号：US20070090484A1

公开(公告)日：2007-04-26

申请号：US11162027

申请日：2005-08-25

申请人： Jae Gon Lee ,  Cher Sian Chua ,  Chew Hoe Ang ,  Liang-Choo Hsia

发明人： Jae Gon Lee ,  Cher Sian Chua ,  Chew Hoe Ang ,  Liang-Choo Hsia

IPC分类号： H01L29/00

CPC分类号： H01L21/823807 ,  H01L21/823878 ,  H01L29/7842

摘要： An integrated circuit stress control system is provided. A gate is formed on a substrate and a channel is formed in the substrate. A source/drain is formed around the gate. A shallow trench isolation is formed in the substrate, the shallow trench isolation producing strain on the channel. A stress suppressing feature is formed in the substrate.

摘要翻译： 提供集成电路应力控制系统。 栅极形成在衬底上，并且沟道形成在衬底中。 源极/漏极围绕栅极形成。 在衬底中形成浅沟槽隔离，通道上的浅沟槽隔离产生应变。 在基板上形成应力抑制特征。

公开(公告)号：US20060252188A1

公开(公告)日：2006-11-09

申请号：US10908328

申请日：2005-05-06

申请人： Purakh Verma ,  Liang-Choo Hsia ,  Dong Kyun Sohn ,  Guowei Zhang ,  Chew Hoe Ang ,  Yun Ling Tan ,  Zhao Lun ,  Jae Gon Lee ,  Yung Fu Chong

发明人： Purakh Verma ,  Liang-Choo Hsia ,  Dong Kyun Sohn ,  Guowei Zhang ,  Chew Hoe Ang ,  Yun Ling Tan ,  Zhao Lun ,  Jae Gon Lee ,  Yung Fu Chong

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L21/82385 ,  H01L21/823814 ,  H01L21/823857 ,  H01L27/11 ,  H01L29/66545 ,  H01L29/7833

摘要： A method and apparatus for manufacturing a semiconductor device is provides a substrate having a first region and a second region. A sacrificial first gate is formed in the first region. Source/drain are formed in the first region. A second region gate dielectric is formed in the second region. A second region gate is formed on the second region gate dielectric. A second region source/drain is formed in the second region. A sacrificial layer is formed over the sacrificial first gate, the source/drain, the first region, and the second region. The sacrificial first gate is exposed. A gate space is formed by removing the sacrificial first gate. A first region gate dielectric is formed in the gate space. A first region gate is formed on the first region gate dielectric. The sacrificial layer is removed.

摘要翻译： 用于制造半导体器件的方法和设备提供具有第一区域和第二区域的衬底。 牺牲第一栅极形成在第一区域中。 源极/漏极形成在第一区域中。 第二区域栅极电介质形成在第二区域中。 第二区域栅极形成在第二区域栅极电介质上。 在第二区域中形成第二区域源极/漏极。 在牺牲第一栅极，源极/漏极，第一区域和第二区域上形成牺牲层。 牺牲的第一个门被暴露。 通过去除牺牲第一栅极形成栅极空间。 在栅极空间中形成第一区域栅极电介质。 第一区栅极形成在第一区栅极电介质上。 牺牲层被去除。

公开(公告)号：US08969151B2

公开(公告)日：2015-03-03

申请号：US12040761

申请日：2008-02-29

申请人： Shyue Seng Tan ,  Lee Wee Teo ,  Chung Foong Tan ,  Jae Gon Lee ,  Elgin Kiok Boone Quek

发明人： Shyue Seng Tan ,  Lee Wee Teo ,  Chung Foong Tan ,  Jae Gon Lee ,  Elgin Kiok Boone Quek

IPC分类号： H01L21/8234 ,  H01L21/8244 ,  H01L27/06 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/00

CPC分类号： H01L27/0629 ,  H01L21/823807 ,  H01L29/7847

摘要： An integrated circuit system that includes: providing a substrate including a first region and a second region; forming a first device over the first region and a resistance device over the second region; forming a first dielectric layer and a second dielectric layer over the substrate; removing a portion of the second dielectric layer; and annealing the integrated circuit system to remove dopant from the resistance device.

摘要翻译： 一种集成电路系统，包括：提供包括第一区域和第二区域的衬底; 在第一区域上形成第一器件，在第二区域上形成电阻器件; 在所述衬底上形成第一电介质层和第二电介质层; 去除所述第二电介质层的一部分; 并退火集成电路系统以从电阻器件去除掺杂剂。

公开(公告)号：US08629503B2

公开(公告)日：2014-01-14

申请号：US13366355

申请日：2012-02-06

申请人： Chung Foong Tan ,  Eng Huat Toh ,  Jae Gon Lee ,  Sanford Chu

发明人： Chung Foong Tan ,  Eng Huat Toh ,  Jae Gon Lee ,  Sanford Chu

IPC分类号： H01L29/78

CPC分类号： H01L29/7835 ,  H01L29/0653 ,  H01L29/66659 ,  H01L29/7848 ,  H01L29/78603 ,  H01L29/78618

摘要： Embodiments of the invention provide an asymmetrical transistor device comprising a semiconductor substrate, a source region, a drain region and a channel region. The channel region is provided between the source and drain regions, the source, drain and channel regions being provided in the substrate. The device has a layer of a buried insulating medium provided below the source region and not below the drain region thereby forming an asymmetrical structure. The layer of buried insulating medium is provided in abutment with a lower surface of the source region.

摘要翻译： 本发明的实施例提供一种包括半导体衬底，源极区，漏极区和沟道区的不对称晶体管器件。 沟道区设置在源极和漏极区之间，源极，漏极和沟道区域设置在衬底中。 该器件具有设置在源极区域下方且不在漏极区域下方的掩埋绝缘介质层，从而形成不对称结构。 掩埋绝缘介质层设置成与源区域的下表面邻接。

公开(公告)号：US08563386B2

公开(公告)日：2013-10-22

申请号：US12947530

申请日：2010-11-16

申请人： Chung Foong Tan ,  Eng Huat Toh ,  Jae Gon Lee ,  Chunshan Yin ,  Lakshmi Bera

发明人： Chung Foong Tan ,  Eng Huat Toh ,  Jae Gon Lee ,  Chunshan Yin ,  Lakshmi Bera

IPC分类号： H01L21/336

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66825

摘要： A method of manufacturing an integrated circuit system includes: providing a substrate having a channel region; forming a gate stack over a portion of the channel region with the gate stack having a floating gate for storing an electrical charge; forming a source recess in the substrate adjacent to the gate stack; and forming a source by layering a first bandgap material in the source recess.

摘要翻译： 一种制造集成电路系统的方法包括：提供具有沟道区的衬底; 在所述沟道区的一部分上形成栅极堆叠，所述栅极堆叠具有用于存储电荷的浮动栅极; 在所述衬底中邻近所述栅极堆叠形成源极凹槽; 以及通过在源凹槽中层叠第一带隙材料来形成源。

公开(公告)号：US20130138848A1

公开(公告)日：2013-05-30

申请号：US13617734

申请日：2012-09-14

申请人： Bub-Chul Jeong ,  Jae Geun Yun ,  Jae Gon Lee ,  Soo Wan Hong

发明人： Bub-Chul Jeong ,  Jae Geun Yun ,  Jae Gon Lee ,  Soo Wan Hong

IPC分类号： G06F13/38

CPC分类号： G06F13/405

摘要： An asynchronous bridge includes a transmission unit and a receiving unit. The transmission unit receives a write valid signal and input data from a master circuit, outputs write addresses increment under control of the write valid signal, sequentially stores the input data in memory cells, as directed by write addresses, and then sequentially outputs the stored input data, as directed by read addresses. The receiving unit receives a read ready signal from a slave circuit, determines whether memory cells are valid, based on the write addresses and the read addresses, and then outputs a read valid signal and the input data, based on the determination.

摘要翻译： 异步桥包括传输单元和接收单元。 发送单元接收写入有效信号并从主电路输入数据，在写入有效信号的控制下输出写入地址增量，按照写入地址的顺序将输入数据依次存储在存储器单元中，然后顺序输出存储的输入 数据，按读取地址指示。 接收单元基于写入地址和读取地址接收来自从属电路的准备就绪信号，确定存储器单元是否有效，然后基于该确定输出读取有效信号和输入数据。