公开(公告)号：US20120188006A1

公开(公告)日：2012-07-26

申请号：US13010249

申请日：2011-01-20

Applicant: Mihai Sanduleanu ,  Ping-Yu Chen

Inventor： Mihai Sanduleanu ,  Ping-Yu Chen

IPC: H04B1/00

CPC classification number: H03H11/1252 ,  H03F3/45183 ,  H03F3/45475 ,  H03F3/45479 ,  H03H11/1234

Abstract: An exemplary filter includes N (≧2) unity gain amplifiers, each with a pair of differential input terminals and a pair of differential output terminals; a pair of filter differential input terminals; a first pair of variable resistances coupling the pair of filter differential input terminals to the pair of differential input terminals of the first unity gain amplifier; N−1 pairs of variable resistances coupling the pairs of differential output terminals of each of the N unity gain amplifiers, other than the last one, to the pairs of differential input terminals of its downstream neighbor; N−1 pairs of variable capacitances coupling the pairs of differential input terminals of each of the N unity gain amplifiers, other than the last one, to the pairs of differential output terminals of its downstream neighbor; and a variable capacitance coupling the pair of differential input terminals of the last unity gain amplifier to each other.

Abstract translation: 示例性滤波器包括N（≥2）个单位增益放大器，每个具有一对差分输入端子和一对差分输出端子; 一对滤波器差分输入端子; 将所述一对滤波器差分输入端耦合到所述第一单位增益放大器的所述一对差分输入端的第一对可变电阻; N-1对可变电阻，将除了最后一个之外的N个单位增益放大器中的每一个的差分输出端子对耦合到其下游邻近的差分输入端子对; N-1对可变电容，将除了最后一个之外的N个单位增益放大器中的每一个的差分输入端的对耦合到其下游邻居的差分输出端对; 以及将最后一个单位增益放大器的该对差分输入端彼此耦合的可变电容。

公开(公告)号：US08344795B2

公开(公告)日：2013-01-01

申请号：US13010249

申请日：2011-01-20

Applicant: Mihai Sanduleanu ,  Ping-Yu Chen

Inventor： Mihai Sanduleanu ,  Ping-Yu Chen

IPC: H03K5/00

CPC classification number: H03H11/1252 ,  H03F3/45183 ,  H03F3/45475 ,  H03F3/45479 ,  H03H11/1234

Abstract: An exemplary filter includes N (≧2) unity gain amplifiers, each with a pair of differential input terminals and a pair of differential output terminals; a pair of filter differential input terminals; a first pair of variable resistances coupling the pair of filter differential input terminals to the pair of differential input terminals of the first unity gain amplifier; N−1 pairs of variable resistances coupling the pairs of differential output terminals of each of the N unity gain amplifiers, other than the last one, to the pairs of differential input terminals of its downstream neighbor; N−1 pairs of variable capacitances coupling the pairs of differential input terminals of each of the N unity gain amplifiers, other than the last one, to the pairs of differential output terminals of its downstream neighbor; and a variable capacitance coupling the pair of differential input terminals of the last unity gain amplifier to each other.

Abstract translation: 示例性滤波器包括N（≥2）个单位增益放大器，每个具有一对差分输入端子和一对差分输出端子; 一对滤波器差分输入端子; 将所述一对滤波器差分输入端耦合到所述第一单位增益放大器的所述一对差分输入端的第一对可变电阻; N-1对可变电阻，将除了最后一个之外的N个单位增益放大器中的每一个的差分输出端子对耦合到其下游邻近的差分输入端子对; N-1对可变电容，将除了最后一个之外的N个单位增益放大器中的每一个的差分输入端的对耦合到其下游邻居的差分输出端对; 以及将最后一个单位增益放大器的该对差分输入端彼此耦合的可变电容。

公开(公告)号：US20060076981A1

公开(公告)日：2006-04-13

申请号：US10523344

申请日：2003-07-23

Applicant: Mihai Sanduleanu

Inventor： Mihai Sanduleanu

IPC: H03D13/00

CPC classification number: H03D13/003 ,  H03D13/00 ,  H03L7/085

Abstract: Known phase detectors have feedbackloops and do not function properly under severe conditions. By providing said phase detectors with difference establishers (1) for establishing differences between input signals and with selectors (2) for selecting one of said differences to be used as an output signal for phase locking purposes, the phase detectors operate better under more severe conditions, with any dead-zone having disappeared. Said selector (2) is a feedbackless selector, then a loop delay no longer exists, the linear range will not get any smaller for higher frequencies, the output jitter will not increase, for sampled input signals. Said selector (2) comprises latches (21,22) and a multiplexer (23). A converter (3) converts input signals into compensated input signals, via a buffer circuit (31,33) coupled to a replica circuit (32,34) per input signal, to provide input signals having substantially equal amplitudes and being compensated with process errors and temperature variations. The difference establisher (1) is based upon moduli or squares.

Abstract translation: 已知的相位检测器有反馈回路，在恶劣条件下不能正常工作。 通过为所述相位检测器提供差分建立器（1），用于建立输入信号与选择器（2）之间的差异，用于选择要用作相位锁定目的的输出信号的所述差异之一，相位检测器在更恶劣的条件下更好地工作 任何死区都消失了。 所述选择器（2）是无反馈选择器，则不再存在环路延迟，对于采样输入信号，线性范围对于较高频率不会变小，输出抖动不会增加。 所述选择器（2）包括锁存器（21,22）和多路复用器（23）。 A转换器（3）经由耦合到每个输入信号的复制电路（32,34）的缓冲电路（31,33）将输入信号转换为补偿的输入信号，以提供具有基本相等幅度的输入信号，并且利用处理误差 和温度变化。 差异建立者（1）基于模数或正方形。

公开(公告)号：US20060250185A1

公开(公告)日：2006-11-09

申请号：US10551027

申请日：2004-03-26

Applicant: Mihai Sanduleanu ,  Eduard Stikvoort

Inventor： Mihai Sanduleanu ,  Eduard Stikvoort

IPC: H03F3/45

CPC classification number: H03F1/3211 ,  H03F1/08 ,  H03F3/45183 ,  H03F3/45928 ,  H03F2200/36 ,  H03F2203/45008 ,  H03F2203/45364 ,  H03F2203/45642 ,  H03F2203/45644 ,  H03F2203/45652 ,  H03F2203/45702

Abstract: A linear amplifier circuit comprising a first differential amplifier (DA 1) having a differential input terminals (I+, I−) for receiving a binary input signal, and a differential output terminals (O+,O−), a second differential amplifier (DA2) having input terminals coupled to the differential input terminals (I+, I−). The amplifier further comprises, a third differential amplifier (DA3) coupled in cascade to the second differential amplifier (DA2) and having its output cross-coupled to the differential output terminals in a feedforward connection, and a capacitor (C) coupled to the third differential amplifier (DA3) for determining an increase of a bandwidth of the linear amplifier, a current flowing through the capacitor (C) being proportional with a derivative of the differential input signal (I+, I−).

Abstract translation: 一种线性放大器电路，包括具有用于接收二进制输入信号的差分输入端（I +，I-）的第一差分放大器（DA 1）和差分输出端（O +，O-），第二差分放大器 ）具有耦合到差分输入端（I +，I-）的输入端。 所述放大器还包括与第二差分放大器（DA 2）级联耦合并使其输出在前馈连接中与差分输出端交叉耦合的第三差分放大器（DA 3），和耦合到 用于确定线性放大器的带宽增加的第三差分放大器（DA 3），流过电容器（C）的电流与差分输入信号（I +，I-）的导数成比例。

公开(公告)号：US20060192594A1

公开(公告)日：2006-08-31

申请号：US10550354

申请日：2004-03-23

Applicant: Mihai Sanduleanu

Inventor： Mihai Sanduleanu

IPC: H03K9/06

CPC classification number: H03L7/087 ,  H03D13/004 ,  H03L7/091 ,  H04L7/033

Abstract: Linear phase detectors comprising circuits (1,2) receiving first and second clock signals (CLKOO, CLK90) for generating first and second control signals (UP,DOWN) for use in clock extractors and data regenerators have large delays due to long path lengths and many operations between input and output (insight). They can be made faster by providing each circuit (1,2) with two parallel latches (10,11,20,21) and a multiplexer (12,22) for multiplexing latch output signals (basic idea). A data signal is supplied to the first circuit (1), and a first circuit output signal is supplied to the second circuit (2). By introducing a third and a fourth circuit (3,4) each also comprising two latches and a multiplexer, a fast linear phase detector has been constructed having a gain which is independent from the number of transitions in the data signal, which is advantageous. Logical circuitry (13,23) of each circuit (1,2,3,4) is coupled to an adder/subtracter (5).

Abstract translation: 线性相位检测器包括接收用于产生用于时钟提取器和数据再生器的第一和第二控制信号（UP，DOWN）的第一和第二时钟信号（CLK00，CLK90）的电路（1,2）由于长路径长度而具有很大的延迟 以及输入和输出之间的许多操作（洞察）。 通过为每个电路（1,2）提供两个并行锁存器（10,11,20,21）和用于复用锁存器输出信号（基本思想）的多路复用器（12,22），可以使其更快。 数据信号被提供给第一电路（1），并且第一电路输出信号被提供给第二电路（2）。 通过引入每个也包括两个锁存器和多路复用器的第三和第四电路（3,4），已经构造了具有独立于数据信号中的转换次数的增益的快速线性相位检测器，这是有利的。 每个电路（1,2,3,4）的逻辑电路（13,23）耦合到加法器/减法器（5）。

公开(公告)号：US20060250161A1

公开(公告)日：2006-11-09

申请号：US10550341

申请日：2004-03-22

Applicant: Mihai Sanduleanu

Inventor： Mihai Sanduleanu

IPC: G01R29/00

CPC classification number: H03L7/089 ,  H03D13/00

Abstract: Linear phase detectors comprising circuits (1,2) receiving reference signals (REF) and first and second clock signals (CLK-Q, CLK-I) for generating first and second (phase) control signals (UP,DOWN) for use in multiplier circuits, demodulators and receivers, have large delays due to long path lengths and many operations between input and output (insight). They can be made faster by providing each circuit (1,2) with two parallel latches (10,11,20,21) and a multiplexer (12,22) for multiplexing latch output signals (basic idea). Said multiplexers generate (frequency control) signals to be supplied to frequency detectors, with a third circuit (3) generating at least one of said (phase) control signals (UP,DOWN). Said third circuit (3) comprises a latch (30) generating said first (phase) control signal (UP), with one of the latches (20) of the second circuit (2) generating the second (phase) control signal (DOWN. Or said third circuit (3) comprises logical circuitry (31-34) comprising four EXOR gates (31-34). A fifth EXOR gate (35) is used for balancing the third circuit (3).

Abstract translation: 线性相位检测器，包括接收参考信号（REF）的电路（1,2）和用于产生用于乘法器的第一和第二（相位）控制信号（UP，DOWN）的第一和第二时钟信号（CLK-Q，CLK-I） 电路，解调器和接收器由于长路径长度和输入和输出之间的许多操作（洞察）而具有大的延迟。 通过为每个电路（1,2）提供两个并行锁存器（10,11,20,21）和用于复用锁存器输出信号（基本思想）的多路复用器（12,22），可以使其更快。 所述多路复用器产生要被提供给频率检测器的（频率控制）信号，第三电路（3）产生所述（相位）控制信号（UP，DOWN）中的至少一个。 所述第三电路（3）包括产生所述第一（相位）控制信号（UP）的锁存器（30），第二电路（2）的锁存器（20）中的一个产生第二（相位）控制信号（DOWN）。 或所述第三电路（3）包括包括四个EXOR门（31-34）的逻辑电路（31-34）。第五EXOR门（35）用于平衡第三电路（3）。

公开(公告)号：US20060220711A1

公开(公告)日：2006-10-05

申请号：US10569124

申请日：2004-08-06

Applicant: Mihai Sanduleanu ,  Dave Van Goor

Inventor： Mihai Sanduleanu ,  Dave Van Goor

IPC: H03L7/06

CPC classification number: H03L7/0896 ,  H03L7/087 ,  H03L7/10 ,  H03L2207/06

Abstract: Charge pump for providing an output current for charging and discharging a filter in accordance with an input signal, said charge pump comprising a first current source connectable with the input signal for driving the current source and adapted to providing a first current equal to a constant current Io plus a variable current Δx, said variable current Δx being directly proportional to the input signal, a second current source connectable with the input signal for driving the current source and adapted to providing a second current equal to the constant current I0 minus said variable current Δx, and an output for providing the output current, wherein said output is connected to both the first and second current source in such a way, that the output current is equal to a difference between the first and second current.

Abstract translation: 电荷泵，用于根据输入信号提供用于对滤波器进行充电和放电的输出电流，所述电荷泵包括可与输入信号连接的第一电流源，用于驱动电流源并适于提供等于恒定电流的第一电流 Io加上可变电流Deltax，所述可变电流Deltax与输入信号成正比，第二电流源可与输入信号连接，用于驱动电流源并适于提供等于恒定电流I 0的第二电流 减去所述可变电流Deltax，以及用于提供输出电流的输出，其中所述输出以这样的方式连接到第一和第二电流源两者，即输出电流等于第一和第二电流源之间的差值 第二电流。

公开(公告)号：US20070146021A1

公开(公告)日：2007-06-28

申请号：US10576554

申请日：2004-10-13

Applicant: Eduard Stikvoort ,  Mihai Sanduleanu

Inventor： Eduard Stikvoort ,  Mihai Sanduleanu

IPC: H03K23/00

CPC classification number: H03K23/44 ,  H03K23/542

Abstract: A frequency divider comprising a first flip-flop (M1, M2, M3, M4) having a first clock input (CI) for receiving a clock signal, the flip-flop further comprising a first set input (Q4) and a first non-inverted output (Q1). The frequency divider further comprises a second flip-flop (M′, M′, M′, M′) having a second clock input (CI) for receiving a second clock signal that is substantially in anti-phase with the clock signal inputted into the first clock input (CI), a second set input coupled to the first non-inverted output (Q1), a second non-inverted output (Q2) and a second inverted output (Q2), the second inverted output (Q2) being coupled to the first set input (Q4).

Abstract translation: 一种分频器，包括具有用于接收时钟信号的第一时钟输入（CI）的第一触发器（M1，M2，M3，M4），所述触发器还包括第一设定输入（Q4）和第一非 - 反相输出（Q1）。 分频器还包括具有第二时钟输入（CI）的第二触发器（M'，M'，M'，M'），用于接收与输入的时钟信号基本上反相的第二时钟信号 第一时钟输入（CI），耦合到第一非反相输出（Q1）的第二组输入，第二非反相输出（Q2）和第二反相输出（Q2），第二反相输出（Q2） 耦合到第一组输入（Q4）。

公开(公告)号：US20060208782A1

公开(公告)日：2006-09-21

申请号：US10550343

申请日：2004-03-22

Applicant: Mihai Sanduleanu ,  Eduard Stikvoort

Inventor： Mihai Sanduleanu ,  Eduard Stikvoort

IPC: H03K3/02

CPC classification number: G11C27/00

Abstract: A track and hold circuit (1) comprising: —a linear amplifier (2) receiving a differential analog signal (D+, D−) and being controlled by a first binary clock signal (H+) having a first phase, —the linear amplifier (2) providing a feed-forward input signal substantially equal with the differential analog signal (D+, D−) to a pseudo latch circuit (3) in the first phase of the first binary clock signal (H+), said pseudo latch circuit (3) being controlled by a second binary clock signal (H−) for memorizing the input signal and providing a differential output signal (LD+, LD−) substantially equal with the input signal during a second phase of the first binary clock signal (H−), the second binary clock signal being substantially in antiphase with the first binary clock signal (H+).

Abstract translation: 一种跟踪和保持电路（1），包括： - 线性放大器（2），其接收差分模拟信号（D +，D-）并由具有第一相位的第一二进制时钟信号（H +）控制， - 线性放大器 2）在第一二进制时钟信号（H +）的第一阶段向伪锁存电路（3）提供与差分模拟信号（D +，D-）基本相等的前馈输入信号，所述伪锁存电路（3） ）由第二二进制时钟信号（H-）控制，用于存储输入信号，并在第一二进制时钟信号（H）的第二相位期间提供与输入信号基本相等的差分输出信号（LD +，LD-） 第二二进制时钟信号基本上与第一二进制时钟信号（H +）反相。

公开(公告)号：US20060050829A1

公开(公告)日：2006-03-09

申请号：US10533058

申请日：2003-10-08

Applicant: Mihai Sanduleanu

Inventor： Mihai Sanduleanu

IPC: H03D3/24

CPC classification number: H03L7/087 ,  H03D13/003 ,  H03L7/091 ,  H03L2207/06 ,  H04L7/0274

Abstract: A Phase Locked Loop (1) used in a data and clock recovery comprising a frequency detector (10) including a quadricorrelator (2), the quadricorrelator (2) comprising a frequency detector including double edge clocked bi-stable circuits (21, 22, 23, 24) coupled to a first multiplexer (31) and to a second multiplexer (32) being controlled by a signal having a same bitrate as the incoming signal (D), and a phase detector (DFF) controlled by a first signal pair (PQ, {overscore (PQ)} provided by the first multiplexer (31) and by a second signal pair (PI, {overscore (PI)}) provided by the second multiplexer (32).

Abstract translation: 一种用于数据和时钟恢复的锁相环（1），包括包括二次相关器（2）的频率检测器（10），所述四相关器（2）包括频率检测器，所述频率检测器包括双边沿时钟双稳态电路（21,22， 耦合到第一多路复用器（31）的第二多路复用器（32）和由具有与输入信号（D）相同的比特率的信号控制的第二多路复用器（32），以及由第一信号对（D）控制的相位检测器 （PQ，{由第一多路复用器（31）提供的PQ）和由第二多路复用器（32）提供的第二信号对（PI，{过滤（PI））提供。