公开(公告)号：US20120170394A1

公开(公告)日：2012-07-05

申请号：US13337386

申请日：2011-12-27

申请人： Min Su KIM ,  Jin Su Park

发明人： Min Su KIM ,  Jin Su Park

IPC分类号： G11C29/04 ,  G11C8/18

CPC分类号： G11C8/04 ,  G11C29/84

摘要： The column address circuit of a semiconductor memory device according to an aspect of the present disclosure includes a column address generation circuit configured to generate an internal dummy clock in response to a data output enable signal, generate an internal clock in response to a read enable signal, generate first count addresses in response to the internal dummy clock, and generate normal count addresses in response to the internal clock after the generation of the first count addresses, where the read enable signal is activated later than the data output enable signal, and a column address output circuit configured to store the first count addresses and the normal addresses and to generate column addresses by synchronizing the first count addresses and the normal addresses with output clocks, respectively.

摘要翻译： 根据本公开的一个方面的半导体存储器件的列地址电路包括：列地址生成电路，被配置为响应于数据输出使能信号产生内部虚拟时钟，响应于读使能信号产生内部时钟 ，响应于内部虚拟时钟产生第一计数地址，并且在产生第一计数地址之后响应于内部时钟产生正常计数地址，其中读使能信号比数据输出使能信号更晚地激活，以及 列地址输出电路，被配置为存储第一计数地址和正常地址，并且分别通过使第一计数地址和正常地址与输出时钟同步来生成列地址。

公开(公告)号：US20150036447A1

公开(公告)日：2015-02-05

申请号：US14202821

申请日：2014-03-10

申请人： Christina WELLS ,  Matt BERZINS ,  Min Su KIM

发明人： Christina WELLS ,  Matt BERZINS ,  Min Su KIM

IPC分类号： H03K5/04 ,  G11C29/02 ,  G11C5/14

CPC分类号： H03K5/04 ,  G11C29/12015

摘要： Exemplary embodiments may disclose a flip-flop circuit for inserting a zero-delay bypass mux including a master circuit which is configured to receive a data input, an input clock signal, and a bypass signal, and output an intermediate signal to a first node; and a slave circuit which is configured to receive the intermediate signal at the first node, the input clock signal, and the bypass signal, and output an output clock signal. The bypass signal controls the slave circuit to output one of a buffered input clock signal and a stretched clock signal as the output clock signal based on a logic level of the bypass signal.

摘要翻译： 示例性实施例可以公开一种用于插入包括被配置为接收数据输入的主电路的零延迟旁路复用器的触发器电路，输入时钟信号和旁路信号，并将中间信号输出到第一节点; 以及被配置为在第一节点处接收中间信号的从属电路，输入时钟信号和旁路信号，并输出输出时钟信号。 旁路信号控制从电路根据旁路信号的逻辑电平输出缓冲输入时钟信号和延时时钟信号之一作为输出时钟信号。

公开(公告)号：US20130088871A1

公开(公告)日：2013-04-11

申请号：US13554904

申请日：2012-07-20

申请人： Kyung Min YUN ,  Min Su KIM ,  Jung Hwa KIM ,  Dong Soo KIM ,  Kyoo Seok KIM

发明人： Kyung Min YUN ,  Min Su KIM ,  Jung Hwa KIM ,  Dong Soo KIM ,  Kyoo Seok KIM

IPC分类号： F21V29/00 ,  F21V5/04 ,  F21V21/00

CPC分类号： F21V17/164 ,  F21S4/28 ,  F21V3/0436 ,  F21V3/062 ,  F21V3/0625 ,  F21V5/007 ,  F21V5/02 ,  F21V23/006 ,  F21V23/06 ,  F21V29/506 ,  F21V29/507 ,  F21V29/51 ,  F21V29/74 ,  F21V29/763 ,  F21V29/777 ,  F21V29/83 ,  F21V31/005 ,  F21W2131/10 ,  F21Y2103/10 ,  F21Y2105/10 ,  F21Y2113/00 ,  F21Y2115/10

摘要： An optical semiconductor lighting apparatus includes a heat sink including a heat dissipation base and a plurality of heat dissipation fins formed on a lower surface of the heat dissipation base; an optical semiconductor device placed on the heat dissipation base; and an optical cover coupled to an upper side of the heat sink to cover the optical semiconductor device. The heat dissipation base is formed with an air flow hole through which upper ends of the heat dissipation fins are exposed.

摘要翻译： 一种光半导体照明装置，具备散热基座和形成在散热基底的下表面上的多个散热片的散热器， 放置在散热基底上的光学半导体器件; 以及耦合到散热器的上侧以覆盖光学半导体器件的光学盖。 散热基部形成有散热片的上端露出的空气流通孔。

公开(公告)号：US20070264571A1

公开(公告)日：2007-11-15

申请号：US11552302

申请日：2006-10-24

申请人： Ji Heon RYU ,  Eun Ju LEE ,  Jaepil LEE ,  Jeong Hee CHOI ,  Min Su KIM ,  Youngjoon SHIN

发明人： Ji Heon RYU ,  Eun Ju LEE ,  Jaepil LEE ,  Jeong Hee CHOI ,  Min Su KIM ,  Youngjoon SHIN

IPC分类号： H01M4/58

CPC分类号： H01M4/62 ,  H01M4/621 ,  H01M4/624 ,  H01M10/052 ,  H01M10/4235 ,  H01M2004/021 ,  H01M2004/027

摘要： Provided is an anode mix for a secondary battery comprising an anode active material, a conductive material and a binder, wherein the anode mix contains 0.01 to 1.0% by weight of alumina having an average particle diameter of less than 1000 nm, based on the total weight of the mix, and a lithium secondary battery comprising the same. Therefore, the present invention can achieve increases in anode active material-conductive material adhesion and anode active material-current collector adhesion which are exerted by a binder, and ultimately can improve lifespan characteristics or cycle characteristics of the battery.

摘要翻译： 提供了一种用于包含阳极活性材料，导电材料和粘合剂的二次电池的阳极混合物，其中所述阳极混合物包含基于总计的平均粒径小于1000nm的0.01至1.0重量％的平均粒径小于1000nm的氧化铝 混合物的重量和包含该混合物的锂二次电池。 因此，本发明可以实现由粘合剂施加的负极活性材料 - 导电材料粘附性和负极活性材料 - 集电器粘合力的增加，并且最终可以提高电池的寿命特性或循环特性。

公开(公告)号：US20070243468A1

公开(公告)日：2007-10-18

申请号：US11552740

申请日：2006-10-25

申请人： Ji Heon RYU ,  Eun Ju LEE ,  Jaepil LEE ,  Jung Eun HYUN ,  Jeong Hee CHOI ,  Min Su KIM ,  Youngjoon SHIN

发明人： Ji Heon RYU ,  Eun Ju LEE ,  Jaepil LEE ,  Jung Eun HYUN ,  Jeong Hee CHOI ,  Min Su KIM ,  Youngjoon SHIN

IPC分类号： H01M10/02

CPC分类号： H01M10/0567 ,  H01M2/1686 ,  H01M4/02 ,  H01M4/62 ,  H01M10/052 ,  H01M10/058 ,  H01M10/4235 ,  H01M2004/021

摘要： Disclosed herein is a lithium secondary battery including a phosphate compound, wherein metal ion impurities incorporated during a fabrication process of the battery are precipitated to thereby prevent electrodeposition of the metal ions on an anode, through the addition of one or more phosphates of Formula I to an electrode, an electrolyte or the surface of a separator: AxH(3−x)PO4   (I) wherein, A is Li, Na or NH4; and O

摘要翻译： 本文公开了一种锂二次电池，其包括磷酸盐化合物，其中在电池的制造过程中引入的金属离子杂质沉淀，从而通过加入一种或多种式I的磷酸盐来防止金属离子在阳极上的电沉积， 电极，电解质或分离器的表面：<？in-line-formula description =“In-line Formulas”end =“lead”？> A 其中，A是Li，Na或NH，其中A是Li，Na或NH，其中A是Li，Na或NH， SUB> 4 和O

公开(公告)号：US20120129691A1

公开(公告)日：2012-05-24

申请号：US13006105

申请日：2011-01-13

申请人： Sung Min CHIN ,  Jong Soo JURNG ,  Gwi Nam BAE ,  Eun Seuk PARK ,  Min Su KIM

发明人： Sung Min CHIN ,  Jong Soo JURNG ,  Gwi Nam BAE ,  Eun Seuk PARK ,  Min Su KIM

IPC分类号： B01J21/06 ,  B01J37/02 ,  B01J19/00 ,  B01J37/08

CPC分类号： B01J35/0013 ,  B01J21/063 ,  B01J23/34 ,  B01J35/008 ,  B01J35/06 ,  B01J37/14 ,  B01J37/349 ,  B01J2208/00203

摘要： Disclosed are an apparatus and method for preparing a manganese oxide-titania catalyst. The apparatus for preparing a manganese oxide-titania catalyst includes: a vaporizer vaporizing a manganese precursor and a titanium precursor; a carrier gas supply line supplying a carrier gas, which carries precursor vapors vaporized by the vaporizer to a reactor, to the vaporizer; an oxygen supply line supplying an oxygen source to the reactor; the reactor reacting the precursor vapors with the oxygen source to synthesize a manganese oxide-titania catalyst; and a collector condensing and collecting the manganese oxide-titania catalyst synthesized in the reactor. And, the method for preparing a manganese oxide-titania catalyst includes: 1) vaporizing a manganese precursor and a titanium precursor; 2) carrying precursor vapors (vapors of the manganese precursor and the titanium precursor) and an oxygen source to a reactor; 3) reacting the precursor vapors and the oxygen source to synthesize a manganese oxide-titania catalyst; and 4) condensing and collecting the manganese oxide-titania catalyst. According to the present disclosure, mass production of manganese oxide-titania catalysts with high decomposition efficiency of organic compounds can be prepared through fewer and continuous processes.

摘要翻译： 公开了一种制备氧化锰 - 二氧化钛催化剂的装置和方法。 用于制备氧化锰 - 二氧化钛催化剂的装置包括：蒸发锰前体和钛前体的蒸发器; 供应载气的载气供应管线，其将由气化器蒸发的前体蒸汽携带到反应器; 向反应器供应氧源的供氧管线; 反应器将前体蒸气与氧源反应以合成氧化锰 - 二氧化钛催化剂; 以及收集器，其收集在反应器中合成的氧化锰 - 二氧化钛催化剂。 而且，制备氧化锰 - 二氧化钛催化剂的方法包括：1）蒸发锰前体和钛前体; 2）将前体蒸汽（锰前体和钛前体的蒸气）和氧源输送到反应器; 3）使前体蒸气和氧源反应合成氧化锰 - 二氧化钛催化剂; 和4）冷凝和收集氧化锰 - 二氧化钛催化剂。 根据本公开，可以通过更少和连续的方法制备具有高分解效率的有机化合物的氧化锰 - 二氧化钛催化剂的批量生产。

公开(公告)号：US20120114068A1

公开(公告)日：2012-05-10

申请号：US13238594

申请日：2011-09-21

申请人： Min Su KIM

发明人： Min Su KIM

IPC分类号： H04L27/00

CPC分类号： H04L25/028

摘要： A flip-flop includes a transmission circuit configured to transmit data to a transmission line in response to a clock signal and a complementary clock signal. The flip-flop further includes a keeper circuit configured to latch data of the transmission line in response to the clock signal and the complementary clock signal to maintain the data of the transmission line constant.

摘要翻译： 触发器包括被配置为响应于时钟信号和互补时钟信号将数据发送到传输线的传输电路。 触发器还包括保持器电路，配置为响应于时钟信号和互补时钟信号来锁存传输线的数据，以保持传输线的数据不变。

公开(公告)号：US20130209352A1

公开(公告)日：2013-08-15

申请号：US13756569

申请日：2013-02-01

申请人： Jong Soo JURNG ,  Eun Seuk PARK ,  Sung Min CHIN ,  Min Su KIM

发明人： Jong Soo JURNG ,  Eun Seuk PARK ,  Sung Min CHIN ,  Min Su KIM

IPC分类号： B01J12/02

CPC分类号： B01J12/02 ,  B01J4/008 ,  B01J19/243 ,  B01J2219/00094 ,  B01J2219/00135 ,  B82Y40/00 ,  Y10S977/773 ,  Y10S977/896

摘要： Disclosed are an apparatus and a method for manufacturing composite nanoparticles. The apparatus comprises: a first precursor supply unit vaporizing a first precursor and supplying it to a reaction unit; a second precursor supply unit vaporizing a second precursor and supplying it to the reaction unit; the reaction unit producing composite nanoparticles by reacting the vaporized first precursor with the vaporized second precursor; an oxygen supply line supplying an oxygen source to the reaction unit; and a collection unit collecting the composite nanoparticles produced by the reaction unit. Since gas phase synthesis occurs in different stages using the U-shaped reaction chamber, aggregation is prevented and composite nanoparticles of uniform size and high specific surface area can be produced easily.

摘要翻译： 公开了一种制造复合纳米颗粒的装置和方法。 该装置包括：第一前体供应单元蒸发第一前体并将其供应到反应单元; 第二前体供应单元蒸发第二前体并将其供应到反应单元; 所述反应单元通过使汽化的第一前体与汽化的第二前体反应来生产复合纳米颗粒; 向所述反应单元供给氧源的供氧线; 以及收集由反应单元生成的复合纳米颗粒的收集单元。 由于使用U形反应室在不同的阶段发生气相合成，因此可以防止聚集，容易产生尺寸均匀，比表面积高的复合纳米颗粒。

公开(公告)号：US20130201767A1

公开(公告)日：2013-08-08

申请号：US13604240

申请日：2012-09-05

申请人： Min Su KIM

发明人： Min Su KIM

IPC分类号： G11C8/00 ,  G11C7/00

CPC分类号： G11C29/76 ,  G11C7/10 ,  G11C7/1069 ,  G11C8/00

摘要： A semiconductor memory apparatus includes: a memory area including a plurality of memory banks having main memory areas configured to transmit and receive data to and from the outside through a plurality of global data lines, respectively, and one or more redundancy memory areas configured to use any one of the global data lines as a common global data line; and a controller configured to control data to be transmitted and received through the common global data line, as a redundancy program mode, a redundancy read mode, or a redundancy erase mode is enabled.

摘要翻译： 半导体存储装置包括：存储区域，包括多个存储器组，其具有分别通过多个全局数据线向外部发送数据和从外部接收数据的主存储区域以及被配置为使用的一个或多个冗余存储区域 全球数据线中的任何一条作为公共全球数据线; 以及被配置为控制通过公共全局数据线发送和接收的数据的控制器，作为冗余编程模式，冗余读取模式或冗余擦除模式。

公开(公告)号：US20130088919A1

公开(公告)日：2013-04-11

申请号：US13618766

申请日：2012-09-14

申请人： Min Su KIM

发明人： Min Su KIM

IPC分类号： G11C16/04

CPC分类号： G11C16/3459 ,  G11C16/26

摘要： A non-volatile memory device includes a memory cell block including a plurality of memory cells, a plurality of page buffer groups including a plurality of page buffers coupled to bit lines of the memory cell block, a pass/fail check circuit coupled to the plurality of page buffers and configured to perform a pass/fail check operation of comparing a total amount of current varying according to verify data sensed from the memory cells and stored in the page buffers with an amount of reference current corresponding to the number of allowed bits, and a control circuit configured to control the pass/fail check circuit by stopping, when a fail signal is generated during the pass/fail check operation currently being performed on a page buffer group among the plurality of page buffer groups, the pass/fail check operation on the remaining page buffer groups.

摘要翻译： 非易失性存储器件包括包括多个存储器单元的存储单元块，多个页缓冲器组，包括耦合到存储单元块的位线的多个页缓冲器，耦合到多个存储单元的通/ 的页缓冲器，并且被配置为执行通过/失败检查操作，以根据从存储器单元感测并存储在页缓冲器中的验证数据变化的电流总量与对应于允许位数的参考电流量进行比较， 以及控制电路，其被配置为通过在所述多个页面缓冲器组中的页面缓冲器组当前正在进行的通过/失败检查操作期间停止生成失败信号时停止所述通过/失败检查电路，所述通过/失败检查 对剩余页面缓冲区进行操作。