公开(公告)号：US20070052857A1

公开(公告)日：2007-03-08

申请号：US11512627

申请日：2006-08-30

申请人： Min-Seok Song ,  Jong-Seon Kim ,  Jae-Youl Lee

发明人： Min-Seok Song ,  Jong-Seon Kim ,  Jae-Youl Lee

IPC分类号： H04N5/45

CPC分类号： G06F3/1431 ,  G09G5/006 ,  G09G2370/025

摘要： A display driver includes a first interface controller, a signal selector, a driver logic unit and a second interface controller. The first interface controller processes a control command transferred through a first interface mode to provide a path control command and a panel control command. The signal selector receives the path control command from the first interface controller, and separates a first video signal and a second video signal from a video signal conforming to a video interface mode. The driver logic unit receives the first video signal from the signal selector and the panel control command from the first interface controller to drive a display panel. The second interface controller outputs the second video signal device through a second interface mode to an external.

摘要翻译： 显示驱动器包括第一接口控制器，信号选择器，驱动器逻辑单元和第二接口控制器。 第一接口控制器处理通过第一接口模式传送的控制命令，以提供路径控制命令和面板控制命令。 信号选择器从第一接口控制器接收路径控制命令，并从符合视频接口模式的视频信号中分离第一视频信号和第二视频信号。 驱动器逻辑单元从第一接口控制器接收来自信号选择器的第一视频信号和面板控制命令以驱动显示面板。 第二接口控制器通过第二接口模式将第二视频信号装置输出到外部。

公开(公告)号：US20080168338A1

公开(公告)日：2008-07-10

申请号：US11829583

申请日：2007-07-27

申请人： Young-Hun Lee ,  Jae-Youl Lee ,  Jong-Seon Kim ,  Kyung-Suc Nah

发明人： Young-Hun Lee ,  Jae-Youl Lee ,  Jong-Seon Kim ,  Kyung-Suc Nah

IPC分类号： G06F11/10

CPC分类号： H04L1/0061

摘要： A parity error detecting circuit includes a first operation unit, a second operation unit, and a shift register. The first operation unit receives a serial data signal and a first signal, performs a logic operation on the two received signals, and outputs the result of the logic operation as the first signal in response to a first clock signal. The shift register shifts the first signal in response to the first clock signal and outputs a second signal. The second operation unit receives the first signal and the second signal, performs a logic operation on the two received signals, and outputs the result of the logic operation in response to a second clock signal.

摘要翻译： 奇偶校验错误检测电路包括第一操作单元，第二操作单元和移位寄存器。 第一操作单元接收串行数据信号和第一信号，对两个接收信号执行逻辑运算，并且响应于第一时钟信号输出逻辑运算的结果作为第一信号。 移位寄存器响应于第一时钟信号移位第一信号并输出​​第二信号。 第二操作单元接收第一信号和第二信号，对两个接收信号执行逻辑运算，并且响应于第二时钟信号输出逻辑运算的结果。

公开(公告)号：US08122334B2

公开(公告)日：2012-02-21

申请号：US11829583

申请日：2007-07-27

申请人： Young-Hun Lee ,  Jae-Youl Lee ,  Jong-Seon Kim ,  Kyung-Suc Nah

发明人： Young-Hun Lee ,  Jae-Youl Lee ,  Jong-Seon Kim ,  Kyung-Suc Nah

IPC分类号： G06F11/10 ,  G06F11/28

CPC分类号： H04L1/0061

摘要： A parity error detecting circuit includes a first operation unit, a second operation unit, and a shift register. The first operation unit receives a serial data signal and a first signal, performs a logic operation on the two received signals, and outputs the result of the logic operation as the first signal in response to a first clock signal. The shift register shifts the first signal in response to the first clock signal and outputs a second signal. The second operation unit receives the first signal and the second signal, performs a logic operation on the two received signals, and outputs the result of the logic operation in response to a second clock signal.

摘要翻译： 奇偶校验错误检测电路包括第一操作单元，第二操作单元和移位寄存器。 第一操作单元接收串行数据信号和第一信号，对两个接收信号执行逻辑运算，并且响应于第一时钟信号输出逻辑运算的结果作为第一信号。 移位寄存器响应于第一时钟信号移位第一信号并输出​​第二信号。 第二操作单元接收第一信号和第二信号，对两个接收信号执行逻辑运算，并且响应于第二时钟信号输出逻辑运算的结果。

公开(公告)号：US20080158424A1

公开(公告)日：2008-07-03

申请号：US11831151

申请日：2007-07-31

申请人： Dae-Jin Park ,  Jong-Seon Kim ,  Jae-Youl Lee ,  Chang-Min Kim

发明人： Dae-Jin Park ,  Jong-Seon Kim ,  Jae-Youl Lee ,  Chang-Min Kim

IPC分类号： H04N5/14

CPC分类号： G09G5/18 ,  G09G3/20 ,  G09G2310/08 ,  G09G2330/06

摘要： A method of deserializing signals output from a master can include generating an indication signal based on occurrence of a first signal pattern input via a data line during a first period and occurrence of a second signal pattern input via a clock line during the first period and enabling a deserializer in response to the indication signal and deserializing serialized video data input via the data line during a second period following the first period, in response to a clock signal input via the clock line during the second period. Related circuits are also disclosed.

摘要翻译： 从主机输出的对信号进行反序列化的方法可以包括：基于在第一时段期间经由数据线输入的第一信号模式的出现以及在第一时段期间通过时钟线输入的第二信号模式的发生产生指示信号，并使能 响应于在所述第二周期期间经由所述时钟线输入的时钟信号，响应于所述指示信号和反序列化在所述第一周期之后的第二周期期间经由所述数据线输入的串行化视频数据的解串器。 还公开了相关电路。

公开(公告)号：US20070018686A1

公开(公告)日：2007-01-25

申请号：US11434960

申请日：2006-05-16

申请人： Jae-Suk Yu ,  Jae-Youl Lee ,  Jong-Seon Kim ,  Kyung-Suc Nah

发明人： Jae-Suk Yu ,  Jae-Youl Lee ,  Jong-Seon Kim ,  Kyung-Suc Nah

IPC分类号： H03K19/094

CPC分类号： H04L25/0298 ,  H04L25/0278

摘要： A low voltage differential signal (LVDS) receiver includes a first receiving unit configured to receive a reference voltage and to responsively generate a first differential signal, and a second receiving unit configured to receive a voltage developed across a variable termination resistor unit having a resistance that is adjustable based on a resistance control code in response to a reference current, and to responsively generate a second differential signal. The LVDS receiver further includes a comparing unit configured to compare the first differential signal with the second differential signal and to responsively generate a counter control signal. The LVDS receiver further includes an up/down counter configured to adjust the resistance control code in response to the counter control signal. The up/down counter is further configured to provide the resistance control code to the variable termination resistor unit. Corresponding methods are also disclosed.

摘要翻译： 低电压差分信号（LVDS）接收机包括：第一接收单元，被配置为接收参考电压并且响应地产生第一差分信号;以及第二接收单元，被配置为接收跨越可变终端电阻器单元产生的电压， 基于响应于参考电流的电阻控制代码可调节，并且响应地产生第二差分信号。 LVDS接收机还包括比较单元，其被配置为将第一差分信号与第二差分信号进行比较，并且响应地产生计数器控制信号。 LVDS接收器还包括一个上/下计数器，配置成响应于计数器控制信号调整电阻控制代码。 上/下计数器还被配置为向可变终端电阻器单元提供电阻控制代码。 还公开了相应的方法。

公开(公告)号：US09007357B2

公开(公告)日：2015-04-14

申请号：US11831151

申请日：2007-07-31

申请人： Dae-Jin Park ,  Jong-Seon Kim ,  Jae-Youl Lee ,  Chang-Min Kim

发明人： Dae-Jin Park ,  Jong-Seon Kim ,  Jae-Youl Lee ,  Chang-Min Kim

IPC分类号： G09G5/00 ,  G09G3/38 ,  G09G3/36 ,  G09G5/18 ,  G09G3/20

CPC分类号： G09G5/18 ,  G09G3/20 ,  G09G2310/08 ,  G09G2330/06

摘要： A method of deserializing signals output from a master can include generating an indication signal based on occurrence of a first signal pattern input via a data line during a first period and occurrence of a second signal pattern input via a clock line during the first period and enabling a deserializer in response to the indication signal and deserializing serialized video data input via the data line during a second period following the first period, in response to a clock signal input via the clock line during the second period. Related circuits are also disclosed.

摘要翻译： 从主机输出的对信号进行反序列化的方法可以包括：基于在第一时段期间经由数据线输入的第一信号模式的出现以及在第一时段期间通过时钟线输入的第二信号模式的发生产生指示信号，并使能 响应于在所述第二周期期间经由所述时钟线输入的时钟信号，响应于所述指示信号和反序列化在所述第一周期之后的第二周期期间经由所述数据线输入的串行化视频数据的解串器。 还公开了相关电路。

公开(公告)号：US07315185B2

公开(公告)日：2008-01-01

申请号：US11434960

申请日：2006-05-16

申请人： Jae-Suk Yu ,  Jae-Youl Lee ,  Jong-Seon Kim ,  Kyung-Suc Nah

发明人： Jae-Suk Yu ,  Jae-Youl Lee ,  Jong-Seon Kim ,  Kyung-Suc Nah

IPC分类号： H03K17/16

CPC分类号： H04L25/0298 ,  H04L25/0278

摘要： A low voltage differential signal (LVDS) receiver includes a first receiving unit configured to receive a reference voltage and to responsively generate a first differential signal, and a second receiving unit configured to receive a voltage developed across a variable termination resistor unit having a resistance that is adjustable based on a resistance control code in response to a reference current, and to responsively generate a second differential signal. The LVDS receiver further includes a comparing unit configured to compare the first differential signal with the second differential signal and to responsively generate a counter control signal. The LVDS receiver further includes an up/down counter configured to adjust the resistance control code in response to the counter control signal. The up/down counter is further configured to provide the resistance control code to the variable termination resistor unit. Corresponding methods are also disclosed.

摘要翻译： 低电压差分信号（LVDS）接收机包括：第一接收单元，被配置为接收参考电压并响应地产生第一差分信号;以及第二接收单元，被配置为接收跨越可变终端电阻器单元产生的电压， 基于响应于参考电流的电阻控制代码可调节，并且响应地产生第二差分信号。 LVDS接收机还包括比较单元，其被配置为将第一差分信号与第二差分信号进行比较，并且响应地产生计数器控制信号。 LVDS接收器还包括一个上/下计数器，配置成响应于计数器控制信号调整电阻控制代码。 上/下计数器还被配置为向可变终端电阻器单元提供电阻控制代码。 还公开了相应的方法。

公开(公告)号：US08424334B2

公开(公告)日：2013-04-23

申请号：US12746199

申请日：2008-12-02

申请人： Byeong-Gyu Kang ,  Jae-Youl Lee ,  Sang-Ho Park

发明人： Byeong-Gyu Kang ,  Jae-Youl Lee ,  Sang-Ho Park

IPC分类号： F25C1/22

CPC分类号： F25C1/04 ,  F25C5/22 ,  F25C2305/022 ,  F25C2400/06 ,  F25C2400/10 ,  F25C2400/12

摘要： Disclosed is an ice making apparatus for a refrigerator, the apparatus comprising a frame having an accommodating space therein, and at least an ice tray detachably installed in the frame and configured to provide a space for containing water to make ice, whereby the ice making apparatus can be easily cleaned up and ice can be easily handled.

摘要翻译： 公开了一种用于冰箱的制冰装置，该装置包括其中具有容纳空间的框架和至少一个可拆卸地安装在框架中并构造成提供用于容纳水以制造冰的空间的冰托盘，由此制冰装置 可以方便地清理干净，并可以轻松处理冰块。

公开(公告)号：US20110005262A1

公开(公告)日：2011-01-13

申请号：US12865916

申请日：2008-12-18

申请人： Byeong-Gyu Kang ,  Jae-Youl Lee ,  Sang-Ho Park

发明人： Byeong-Gyu Kang ,  Jae-Youl Lee ,  Sang-Ho Park

IPC分类号： F25C5/18

CPC分类号： F25D23/04 ,  F25C5/182 ,  F25D25/025 ,  F25D2323/023 ,  F25D2325/021

摘要： A refrigerator comprises: an opening disposed at one side of a door; an ice bank disposed on a rear surface of the door, and configured to be drawn out through the opening, for storing ice pieces; a guide unit for guiding the ice bank to be drawn out; and a volume control unit for changing a volume of the ice bank step by step. A volume of the ice bank is varied according to users necessity. This solves a users inconvenience to make ice pieces a plurality of times, for example, in summer when a large amount of ice pieces are required.

摘要翻译： 冰箱包括：设置在门一侧的开口; 布置在所述门的后表面上并被构造成通过所述开口被拉出以用于存储冰块的冰块; 引导单元，用于引导要被抽出的冰库; 以及音量控制单元，用于逐步改变冰块的体积。 冰库的数量根据用户的需要而变化。 这样可以解决使用者造成冰块多次的不便，例如在需要大量冰块的夏季时。

公开(公告)号：US07359270B2

公开(公告)日：2008-04-15

申请号：US10875613

申请日：2004-06-25

申请人： Jae-Youl Lee

发明人： Jae-Youl Lee

IPC分类号： G11C7/00 ,  G11C7/04

CPC分类号： G11C11/40626 ,  G11C11/406 ,  G11C11/40615 ,  G11C2211/4061

摘要： A self refresh period signal generating device includes an internal temperature sensor; an extended mode register set for storing a first temperature code which corresponds to temperature measured by an external temperature sensor; a selection means for selecting one of the first temperature code included in the extended mode register set and a second temperature code which corresponds to temperature measured by the internal temperature sensor; and a self refresh period signal generating means for generating a temperature compensated self refresh period signal in response to an output signal from the selection means.

摘要翻译： 自刷新周期信号发生装置包括内部温度传感器; 扩展模式寄存器，用于存储对应于由外部温度传感器测量的温度的第一温度代码; 选择装置，用于选择包括在扩展模式寄存器组中的第一温度代码中的一个和对应于由内部温度传感器测量的温度的第二温度代码; 以及自刷新周期信号发生装置，用于响应于来自选择装置的输出信号产生温度补偿的自刷新周期信号。