公开(公告)号：US20070052857A1

公开(公告)日：2007-03-08

申请号：US11512627

申请日：2006-08-30

申请人： Min-Seok Song ,  Jong-Seon Kim ,  Jae-Youl Lee

发明人： Min-Seok Song ,  Jong-Seon Kim ,  Jae-Youl Lee

IPC分类号： H04N5/45

CPC分类号： G06F3/1431 ,  G09G5/006 ,  G09G2370/025

摘要： A display driver includes a first interface controller, a signal selector, a driver logic unit and a second interface controller. The first interface controller processes a control command transferred through a first interface mode to provide a path control command and a panel control command. The signal selector receives the path control command from the first interface controller, and separates a first video signal and a second video signal from a video signal conforming to a video interface mode. The driver logic unit receives the first video signal from the signal selector and the panel control command from the first interface controller to drive a display panel. The second interface controller outputs the second video signal device through a second interface mode to an external.

摘要翻译： 显示驱动器包括第一接口控制器，信号选择器，驱动器逻辑单元和第二接口控制器。 第一接口控制器处理通过第一接口模式传送的控制命令，以提供路径控制命令和面板控制命令。 信号选择器从第一接口控制器接收路径控制命令，并从符合视频接口模式的视频信号中分离第一视频信号和第二视频信号。 驱动器逻辑单元从第一接口控制器接收来自信号选择器的第一视频信号和面板控制命令以驱动显示面板。 第二接口控制器通过第二接口模式将第二视频信号装置输出到外部。

公开(公告)号：US09007357B2

公开(公告)日：2015-04-14

申请号：US11831151

申请日：2007-07-31

申请人： Dae-Jin Park ,  Jong-Seon Kim ,  Jae-Youl Lee ,  Chang-Min Kim

发明人： Dae-Jin Park ,  Jong-Seon Kim ,  Jae-Youl Lee ,  Chang-Min Kim

IPC分类号： G09G5/00 ,  G09G3/38 ,  G09G3/36 ,  G09G5/18 ,  G09G3/20

CPC分类号： G09G5/18 ,  G09G3/20 ,  G09G2310/08 ,  G09G2330/06

摘要： A method of deserializing signals output from a master can include generating an indication signal based on occurrence of a first signal pattern input via a data line during a first period and occurrence of a second signal pattern input via a clock line during the first period and enabling a deserializer in response to the indication signal and deserializing serialized video data input via the data line during a second period following the first period, in response to a clock signal input via the clock line during the second period. Related circuits are also disclosed.

摘要翻译： 从主机输出的对信号进行反序列化的方法可以包括：基于在第一时段期间经由数据线输入的第一信号模式的出现以及在第一时段期间通过时钟线输入的第二信号模式的发生产生指示信号，并使能 响应于在所述第二周期期间经由所述时钟线输入的时钟信号，响应于所述指示信号和反序列化在所述第一周期之后的第二周期期间经由所述数据线输入的串行化视频数据的解串器。 还公开了相关电路。

公开(公告)号：US07315185B2

公开(公告)日：2008-01-01

申请号：US11434960

申请日：2006-05-16

申请人： Jae-Suk Yu ,  Jae-Youl Lee ,  Jong-Seon Kim ,  Kyung-Suc Nah

发明人： Jae-Suk Yu ,  Jae-Youl Lee ,  Jong-Seon Kim ,  Kyung-Suc Nah

IPC分类号： H03K17/16

CPC分类号： H04L25/0298 ,  H04L25/0278

摘要： A low voltage differential signal (LVDS) receiver includes a first receiving unit configured to receive a reference voltage and to responsively generate a first differential signal, and a second receiving unit configured to receive a voltage developed across a variable termination resistor unit having a resistance that is adjustable based on a resistance control code in response to a reference current, and to responsively generate a second differential signal. The LVDS receiver further includes a comparing unit configured to compare the first differential signal with the second differential signal and to responsively generate a counter control signal. The LVDS receiver further includes an up/down counter configured to adjust the resistance control code in response to the counter control signal. The up/down counter is further configured to provide the resistance control code to the variable termination resistor unit. Corresponding methods are also disclosed.

摘要翻译： 低电压差分信号（LVDS）接收机包括：第一接收单元，被配置为接收参考电压并响应地产生第一差分信号;以及第二接收单元，被配置为接收跨越可变终端电阻器单元产生的电压， 基于响应于参考电流的电阻控制代码可调节，并且响应地产生第二差分信号。 LVDS接收机还包括比较单元，其被配置为将第一差分信号与第二差分信号进行比较，并且响应地产生计数器控制信号。 LVDS接收器还包括一个上/下计数器，配置成响应于计数器控制信号调整电阻控制代码。 上/下计数器还被配置为向可变终端电阻器单元提供电阻控制代码。 还公开了相应的方法。

公开(公告)号：US08122334B2

公开(公告)日：2012-02-21

申请号：US11829583

申请日：2007-07-27

申请人： Young-Hun Lee ,  Jae-Youl Lee ,  Jong-Seon Kim ,  Kyung-Suc Nah

发明人： Young-Hun Lee ,  Jae-Youl Lee ,  Jong-Seon Kim ,  Kyung-Suc Nah

IPC分类号： G06F11/10 ,  G06F11/28

CPC分类号： H04L1/0061

摘要： A parity error detecting circuit includes a first operation unit, a second operation unit, and a shift register. The first operation unit receives a serial data signal and a first signal, performs a logic operation on the two received signals, and outputs the result of the logic operation as the first signal in response to a first clock signal. The shift register shifts the first signal in response to the first clock signal and outputs a second signal. The second operation unit receives the first signal and the second signal, performs a logic operation on the two received signals, and outputs the result of the logic operation in response to a second clock signal.

摘要翻译： 奇偶校验错误检测电路包括第一操作单元，第二操作单元和移位寄存器。 第一操作单元接收串行数据信号和第一信号，对两个接收信号执行逻辑运算，并且响应于第一时钟信号输出逻辑运算的结果作为第一信号。 移位寄存器响应于第一时钟信号移位第一信号并输出​​第二信号。 第二操作单元接收第一信号和第二信号，对两个接收信号执行逻辑运算，并且响应于第二时钟信号输出逻辑运算的结果。

公开(公告)号：US20080158424A1

公开(公告)日：2008-07-03

申请号：US11831151

申请日：2007-07-31

申请人： Dae-Jin Park ,  Jong-Seon Kim ,  Jae-Youl Lee ,  Chang-Min Kim

发明人： Dae-Jin Park ,  Jong-Seon Kim ,  Jae-Youl Lee ,  Chang-Min Kim

IPC分类号： H04N5/14

CPC分类号： G09G5/18 ,  G09G3/20 ,  G09G2310/08 ,  G09G2330/06

摘要： A method of deserializing signals output from a master can include generating an indication signal based on occurrence of a first signal pattern input via a data line during a first period and occurrence of a second signal pattern input via a clock line during the first period and enabling a deserializer in response to the indication signal and deserializing serialized video data input via the data line during a second period following the first period, in response to a clock signal input via the clock line during the second period. Related circuits are also disclosed.

摘要翻译： 从主机输出的对信号进行反序列化的方法可以包括：基于在第一时段期间经由数据线输入的第一信号模式的出现以及在第一时段期间通过时钟线输入的第二信号模式的发生产生指示信号，并使能 响应于在所述第二周期期间经由所述时钟线输入的时钟信号，响应于所述指示信号和反序列化在所述第一周期之后的第二周期期间经由所述数据线输入的串行化视频数据的解串器。 还公开了相关电路。

公开(公告)号：US20070018686A1

公开(公告)日：2007-01-25

申请号：US11434960

申请日：2006-05-16

申请人： Jae-Suk Yu ,  Jae-Youl Lee ,  Jong-Seon Kim ,  Kyung-Suc Nah

发明人： Jae-Suk Yu ,  Jae-Youl Lee ,  Jong-Seon Kim ,  Kyung-Suc Nah

IPC分类号： H03K19/094

CPC分类号： H04L25/0298 ,  H04L25/0278

摘要： A low voltage differential signal (LVDS) receiver includes a first receiving unit configured to receive a reference voltage and to responsively generate a first differential signal, and a second receiving unit configured to receive a voltage developed across a variable termination resistor unit having a resistance that is adjustable based on a resistance control code in response to a reference current, and to responsively generate a second differential signal. The LVDS receiver further includes a comparing unit configured to compare the first differential signal with the second differential signal and to responsively generate a counter control signal. The LVDS receiver further includes an up/down counter configured to adjust the resistance control code in response to the counter control signal. The up/down counter is further configured to provide the resistance control code to the variable termination resistor unit. Corresponding methods are also disclosed.

摘要翻译： 低电压差分信号（LVDS）接收机包括：第一接收单元，被配置为接收参考电压并且响应地产生第一差分信号;以及第二接收单元，被配置为接收跨越可变终端电阻器单元产生的电压， 基于响应于参考电流的电阻控制代码可调节，并且响应地产生第二差分信号。 LVDS接收机还包括比较单元，其被配置为将第一差分信号与第二差分信号进行比较，并且响应地产生计数器控制信号。 LVDS接收器还包括一个上/下计数器，配置成响应于计数器控制信号调整电阻控制代码。 上/下计数器还被配置为向可变终端电阻器单元提供电阻控制代码。 还公开了相应的方法。

公开(公告)号：US20080168338A1

公开(公告)日：2008-07-10

申请号：US11829583

申请日：2007-07-27

申请人： Young-Hun Lee ,  Jae-Youl Lee ,  Jong-Seon Kim ,  Kyung-Suc Nah

发明人： Young-Hun Lee ,  Jae-Youl Lee ,  Jong-Seon Kim ,  Kyung-Suc Nah

IPC分类号： G06F11/10

CPC分类号： H04L1/0061

摘要： A parity error detecting circuit includes a first operation unit, a second operation unit, and a shift register. The first operation unit receives a serial data signal and a first signal, performs a logic operation on the two received signals, and outputs the result of the logic operation as the first signal in response to a first clock signal. The shift register shifts the first signal in response to the first clock signal and outputs a second signal. The second operation unit receives the first signal and the second signal, performs a logic operation on the two received signals, and outputs the result of the logic operation in response to a second clock signal.

摘要翻译： 奇偶校验错误检测电路包括第一操作单元，第二操作单元和移位寄存器。 第一操作单元接收串行数据信号和第一信号，对两个接收信号执行逻辑运算，并且响应于第一时钟信号输出逻辑运算的结果作为第一信号。 移位寄存器响应于第一时钟信号移位第一信号并输出​​第二信号。 第二操作单元接收第一信号和第二信号，对两个接收信号执行逻辑运算，并且响应于第二时钟信号输出逻辑运算的结果。

公开(公告)号：US07804497B2

公开(公告)日：2010-09-28

申请号：US11513299

申请日：2006-08-30

申请人： Min-Seok Song ,  Jong-Seon Kim

发明人： Min-Seok Song ,  Jong-Seon Kim

IPC分类号： G09G5/00

CPC分类号： G06F3/1431 ,  G09G5/006 ,  G09G2330/022 ,  G09G2330/06

摘要： A display driving circuit includes a first interface unit, a signal discriminating circuit, a signal distributing circuit, a driver logic circuit and a synchronization processing unit. The first interface unit receives a first signal through a first interface from a host. The signal discriminating circuit discriminates whether the first signal corresponds to a first video signal or a second video signal. The signal distributing circuit divides the first signal into the first and second video signals based on a discrimination result of the signal discriminating circuit. The driver logic circuit drives a first display panel based on the first video signal. The second interface unit converts the second video signal into a second signal and provides the second signal through a second interface to an external display device. The synchronization processing unit receives a synchronization signal from the external display device and provides the synchronization signal to the host.

摘要翻译： 显示驱动电路包括第一接口单元，信号鉴别电路，信号分配电路，驱动器逻辑电路和同步处理单元。 第一接口单元通过来自主机的第一接口接收第一信号。 信号识别电路鉴别第一信号是否对应于第一视频信号或第二视频信号。 信号分配电路根据信号识别电路的鉴别结果，将第一信号划分为第一和第二视频信号。 驱动器逻辑电路基于第一视频信号驱动第一显示面板。 第二接口单元将第二视频信号转换为第二信号，并通过第二接口将第二信号提供给外部显示设备。 同步处理单元从外部显示装置接收同步信号并向主机提供同步信号。

公开(公告)号：US20070057865A1

公开(公告)日：2007-03-15

申请号：US11513299

申请日：2006-08-30

申请人： Min-Seok Song ,  Jong-Seon Kim

发明人： Min-Seok Song ,  Jong-Seon Kim

IPC分类号： G09G5/00

CPC分类号： G06F3/1431 ,  G09G5/006 ,  G09G2330/022 ,  G09G2330/06

摘要： A display driving circuit includes a first interface unit, a signal discriminating circuit, a signal distributing circuit, a driver logic circuit and a synchronization processing unit. The first interface unit receives a first signal through a first interface from a host. The signal discriminating circuit discriminates whether the first signal corresponds to a first video signal or a second video signal. The signal distributing circuit divides the first signal into the first and second video signals based on a discrimination result of the signal discriminating circuit. The driver logic circuit drives a first display panel based on the first video signal. The second interface unit converts the second video signal into a second signal and provides the second signal through a second interface to an external display device. The synchronization processing unit receives a synchronization signal from the external display device and provides the synchronization signal to the host.

摘要翻译： 显示驱动电路包括第一接口单元，信号鉴别电路，信号分配电路，驱动器逻辑电路和同步处理单元。 第一接口单元通过来自主机的第一接口接收第一信号。 信号识别电路鉴别第一信号是否对应于第一视频信号或第二视频信号。 信号分配电路根据信号识别电路的鉴别结果，将第一信号划分为第一和第二视频信号。 驱动器逻辑电路基于第一视频信号驱动第一显示面板。 第二接口单元将第二视频信号转换为第二信号，并通过第二接口将第二信号提供给外部显示设备。 同步处理单元从外部显示装置接收同步信号并向主机提供同步信号。

公开(公告)号：US08581919B2

公开(公告)日：2013-11-12

申请号：US12727631

申请日：2010-03-19

申请人： Yong-Yun Park ,  Won-Gab Jung ,  Jong-Seon Kim ,  Sang-Woo Kim ,  Hae-Yong Ahn

发明人： Yong-Yun Park ,  Won-Gab Jung ,  Jong-Seon Kim ,  Sang-Woo Kim ,  Hae-Yong Ahn

IPC分类号： G09G5/36

CPC分类号： G09G3/3611 ,  G09G5/395 ,  G09G5/397 ,  G09G2320/0252 ,  G09G2340/02 ,  G09G2360/18

摘要： A display controller is provided. The display controller includes an external memory and a timing controller which compresses current frame data to generate front first in-first out (FIFO) input data, temporarily stores the front FIFO input data and writes the front FIFO input data to the external memory in a burst mode, and reads data from the external memory in the burst mode, temporarily stores the read data as back FIFO output data, and decodes the back FIFO output data to output previous frame data.

摘要翻译： 提供显示控制器。 显示控制器包括外部存储器和定时控制器，其压缩当前帧数据以产生前置先进先出（FIFO）输入数据，临时存储前FIFO输入数据，并将前FIFO输入数据写入外部存储器 突发模式，并且以突发模式从外部存储器读取数据，将读取的数据临时存储为后向FIFO输出数据，并且解码后退FIFO输出数据以输出先前的帧数据。