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    Flip-flops and electronic digital circuits including the same
    1.
    发明申请
    Flip-flops and electronic digital circuits including the same 有权
    触发器和包括其的电子数字电路

    公开(公告)号：US20080024183A1

    公开(公告)日：2008-01-31

    申请号：US11819388

    申请日：2007-06-27

    申请人： Min-Su Kim ,  Bai-Sun Kong

    发明人： Min-Su Kim ,  Bai-Sun Kong

    IPC分类号： H03K3/0233

    CPC分类号： H03K3/356121 ,  H03K3/356147 ,  H03K3/356191

    摘要： A flip-flop includes a first circuit receiving a clock signal and the first signal and transitioning the first and second output signals to a first level when the clock signal goes to an active level, and a second circuit transitioning the first signal to the first level after the first and second output signals go to the first level. The first circuit transfers first and second input signals to the first and second output terminals from first and second input terminals when the clock signal is at the active level and the first signal is at the first level.

    摘要翻译： 触发器包括接收时钟信号和第一信号的第一电路，并且当时钟信号进入有效电平时，将第一和第二输出信号转换到第一电平，第二电路将第一信号转换到第一电平 在第一和第二输出信号进入第一级之后。 当时钟信号处于有效电平并且第一信号处于第一电平时，第一电路将第一和第二输入信号从第一和第二输入端传送到第一和第二输出端。

    High speed flip-flop
    2.
    发明授权
    High speed flip-flop 失效
    高速触发器

    公开(公告)号：US07528630B2

    公开(公告)日：2009-05-05

    申请号：US11970629

    申请日：2008-01-08

    申请人： Min-Su Kim ,  Bai-Sun Kong

    发明人： Min-Su Kim ,  Bai-Sun Kong

    IPC分类号： H03K19/00

    CPC分类号： H03K3/356121

    摘要： A flip-flop circuit includes a precharging circuit which precharges a first circuit node in response to a first pulse signal and an estimation circuit that receives an input signal and a second pulse signal. The estimation circuit discharges the voltage from the first node in response to the input signal on activation of the second pulse signal. The first pulse signal is synchronized to a clock signal and the second pulse signal is delayed from the first pulse signal.

    摘要翻译： 触发器电路包括：预充电电路，其响应于第一脉冲信号对第一电路节点进行预充电;以及估计电路，其接收输入信号和第二脉冲信号。 在激活第二脉冲信号时，估计电路响应于输入信号从第一节点放电电压。 第一脉冲信号与时钟信号同步，第二脉冲信号从第一脉冲信号延迟。

    Flip-flops and electronic digital circuits including the same
    3.
    发明授权
    Flip-flops and electronic digital circuits including the same 有权
    触发器和包括其的电子数字电路

    公开(公告)号：US07504871B2

    公开(公告)日：2009-03-17

    申请号：US11819388

    申请日：2007-06-27

    申请人： Min-Su Kim ,  Bai-Sun Kong

    发明人： Min-Su Kim ,  Bai-Sun Kong

    IPC分类号： H03K3/00

    CPC分类号： H03K3/356121 ,  H03K3/356147 ,  H03K3/356191

    摘要： A flip-flop includes a first circuit receiving a clock signal and the first signal and transitioning the first and second output signals to a first level when the clock signal goes to an active level, and a second circuit transitioning the first signal to the first level after the first and second output signals go to the first level. The first circuit transfers first and second input signals to the first and second output terminals from first and second input terminals when the clock signal is at the active level and the first signal is at the first level.

    摘要翻译： 触发器包括接收时钟信号和第一信号的第一电路，并且当时钟信号进入有效电平时，将第一和第二输出信号转换到第一电平，第二电路将第一信号转换到第一电平 在第一和第二输出信号进入第一级之后。 当时钟信号处于有效电平并且第一信号处于第一电平时，第一电路将第一和第二输入信号从第一和第二输入端传送到第一和第二输出端。

    Semiconductor device
    4.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US09837992B2

    公开(公告)日：2017-12-05

    申请号：US15077438

    申请日：2016-03-22

    申请人： Hyun-Chul Hwang ,  Min-Su Kim

    发明人： Hyun-Chul Hwang ,  Min-Su Kim

    IPC分类号： H03K3/289 ,  H03K3/012 ,  H03K3/356

    CPC分类号： H03K3/012 ,  H03K3/356191

    摘要： A semiconductor circuit includes a first circuit determining a voltage of a first node in response to the clock signal and the input data signal, a first latch determining a voltage of a second node in response to the clock signal and the voltage of the first node, and a second circuit determining a voltage of a third node in response to the clock signal and the voltage of the second node. The output data signal is provided in response to the voltage of the third node, the clock signal controls a flip-flop operation with respect to the input data signal and the output data signal, and respective voltages are maintained constant at the first node, second node and third node regardless of level transitions in the clock signal so long as a level of the input data signal is maintained constant.

    Semiconductor device
    5.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09450584B2

    公开(公告)日：2016-09-20

    申请号：US14870351

    申请日：2015-09-30

    申请人： Min-Su Kim

    发明人： Min-Su Kim

    IPC分类号： H03K19/0175 ,  H03K19/0185 ,  H03K19/20 ,  H03K3/356

    CPC分类号： H03K19/018507 ,  H03K3/012 ,  H03K3/356 ,  H03K3/356173 ,  H03K19/0016 ,  H03K19/20

    摘要： A semiconductor device includes a first circuit applying an enable signal having a first logic level and a clock signal having the first logic level, supplying a first voltage to a first node and converting a voltage level of the first node into a second logic level different from the first logic level, and a second circuit applying an enable signal having the second logic level and a clock signal having the first logic level, supplying a second voltage to a second node different from the first node and converting a voltage level of the second node into the second logic level. The second circuit includes an operation circuit performing a NAND operation on the logic level of the enable signal and the voltage level of the second node, and a switch turned on in response to an output of the operation circuit and supplying the second voltage to the second node.

    摘要翻译： 半导体器件包括施加具有第一逻辑电平的使能信号和具有第一逻辑电平的时钟信号的第一电路，向第一节点提供第一电压并将第一节点的电压电平转换成不同于第一逻辑电平的第二逻辑电平 第一逻辑电平，以及施加具有第二逻辑电平的使能信号和具有第一逻辑电平的时钟信号的第二电路，向不同于第一节点的第二节点提供第二电压，并且转换第二节点的电压电平 进入第二个逻辑水平。 第二电路包括对使能信号的逻辑电平和第二节点的电压电平执行NAND运算的运算电路，以及响应于运算电路的输出而导通的开关，并将第二电压提供给第二电路 节点。

    Polarizer and liquid crystal display using the same
    6.
    发明授权
    Polarizer and liquid crystal display using the same 有权
    偏光镜和液晶显示器使用相同

    公开(公告)号：US08755008B2

    公开(公告)日：2014-06-17

    申请号：US13431702

    申请日：2012-03-27

    申请人： Jae-Hong Park ,  Jong-Sung Park ,  Min-Su Kim ,  Sung-Hyun Kim

    发明人： Jae-Hong Park ,  Jong-Sung Park ,  Min-Su Kim ,  Sung-Hyun Kim

    IPC分类号： G02F1/1335

    CPC分类号： G02B5/3033 ,  G02B1/105 ,  G02B1/11 ,  G02B1/14 ,  G02B1/16 ,  G02F1/133528 ,  G02F1/13452

    摘要： Disclosed is a liquid crystal display and a polarizing plate used in the same. The liquid crystal display includes a liquid crystal cell and a first polarizing plate and a second polarizing plate respectively provided on each side of the liquid crystal cell. The first polarizing plate and the second polarizing plate each includes a polyvinyl alcohol polarizing film and protective films provided on both sides of the polyvinyl alcohol polarizing film, the protective films that are provided on surfaces opposite to the liquid crystal cell the first polarizing plate and the second polarizing plate each has the vapor transmissivity of 100 g/m Day or less, and the protective films that are provided on surfaces abutting the liquid crystal cell of the first polarizing plate and the second polarizing plate each has the vapor transmissivity of more than 1,500 g/m Day. When the protective films that are provided on surfaces opposite to the liquid crystal cell of the first polarizing plate and the second polarizing plate each has a UV absorption ability, the protective films that are provided on surfaces abutting the liquid crystal cell of the first polarizing plate and the second polarizing plate each has the vapor transmissivity of more than 200 g/m Day.

    摘要翻译： 公开了一种液晶显示器和偏光板。 液晶显示器包括分别设置在液晶单元的每一侧的液晶单元和第一偏振板和第二偏振板。 第一偏振板和第二偏振板各自包括聚乙烯醇偏振片和设置在聚乙烯醇偏振片两侧的保护膜，保护膜设置在与液晶单元相反的表面上，第一偏振片和 第二偏光板的蒸气透过率为100g / m以下，并且设置在与第一偏振片和第二偏光板的液晶单元抵接的面上的保护膜的蒸气透过率为1500以上 g / m天。 当设置在与第一偏振片和第二偏振片的液晶单元相对的表面上的保护膜各自具有UV吸收能力时，设置在与第一偏振板的液晶单元相邻的表面上的保护膜 并且第二偏振板各自具有大于200g / m 2日的蒸汽透过率。

    Dynamic domino circuit and integrated circuit including the same
    10.
    发明授权
    Dynamic domino circuit and integrated circuit including the same 有权
    动态多米诺骨牌电路和集成电路包括相同

    公开(公告)号：US07932750B2

    公开(公告)日：2011-04-26

    申请号：US12769000

    申请日：2010-04-28

    申请人： Min-Su Kim

    发明人： Min-Su Kim

    IPC分类号： H03K19/00

    CPC分类号： H03K19/0963

    摘要： A dynamic domino circuit includes a clock generator and a domino circuit. The clock generator generates a pulse signal and a plurality of internal clock signals based on a global clock signal. Phases of the plurality of internal clock signals are sequentially delayed. The domino circuit sequentially performs a plurality of logic operations based on a plurality of input signals, the pulse signal and the plurality of internal clock signals and generates an output signal in synchronization with the pulse signal. The dynamic domino circuit may provide an effective interface with static logics.

    摘要翻译： 动态多米诺骨牌电路包括时钟发生器和多米诺骨牌电路。 时钟发生器基于全局时钟信号产生脉冲信号和多个内部时钟信号。 多个内部时钟信号的相位被依次延迟。 多米诺骨电路基于多个输入信号，脉冲信号和多个内部时钟信号顺序执行多个逻辑运算，并与脉冲信号同步地产生输出信号。 动态多米诺骨牌电路可以提供静态逻辑的有效接口。