公开(公告)号：US06444566B1

公开(公告)日：2002-09-03

申请号：US09845481

申请日：2001-04-30

申请人： Ming Huan Tsai ,  Jyh Huei Chen ,  Chu Yun Fu ,  Hun Jan Tao

发明人： Ming Huan Tsai ,  Jyh Huei Chen ,  Chu Yun Fu ,  Hun Jan Tao

IPC分类号： H01L214763

CPC分类号： H01L21/76897 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834

摘要： Borderless contacts are used in integrated circuits in order to conserve chip real estate. As part of the process for manufacturing borderless contacts, an etch-stopping layer of silicon nitride is first laid over the area that is to be contacted. Investigation has now shown that this can lead to damage to the silicon at the edges of the via. The present invention eliminates this damage by introducing a buffer layer between the silicon surface and said sidon nitride layer. Suitable materials for the buffer layer that have been found to be infective include silicon oxide and silicon oxynitride with the latter offering some ditional advantages over the former. Experimental data confirming the effectiveness of the buffer layer are provided, together with a process for its manufacture.

摘要翻译： 无边界接触用于集成电路，以节省芯片的不动产。 作为制造无边界接触的工艺的一部分，首先将氮化硅的蚀刻停止层铺设在要接触的区域上。 现在调查显示，这可能导致在通孔边缘的硅损坏。 本发明通过在硅表面和所述侧氮化物层之间引入缓冲层来消除这种损害。 已经发现感染的缓冲层的合适材料包括氧化硅和氮氧化硅，后者提供了比前者更多的优点。 提供确认缓冲层有效性的实验数据及其制造方法。

公开(公告)号：US06630398B2

公开(公告)日：2003-10-07

申请号：US10213588

申请日：2002-08-07

申请人： Ming Huan Tsai ,  Jyh Huei Chen ,  Chu Yun Fu ,  Hun Jan Tao

发明人： Ming Huan Tsai ,  Jyh Huei Chen ,  Chu Yun Fu ,  Hun Jan Tao

IPC分类号： H01L214763

CPC分类号： H01L21/76897 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834

摘要： Borderless contacts are used in integrated circuits in order to conserve chip real estate. As part of the process for manufacturing borderless contacts, an etch-stopping layer of silicon nitride is first laid over the area that is to be contacted Investigation has now shown that this can lead to damage to the silicon at the edges of the via. The present invention eliminates this damage by introducing a buffer layer between the silicon surface and said silicon nitride layer. Suitable materials for the buffer layer that have been found to be effective include silicon oxide and silicon oxynitride with the latter offering some additional advantages over the former. Experimental data confirming the effectiveness of the buffer layer are provided, together with a process for its manufacture.

公开(公告)号：US06316348B1

公开(公告)日：2001-11-13

申请号：US09838627

申请日：2001-04-20

申请人： Chu Yun Fu ,  Chia Shiung Tsai ,  Syun-Ming Jang

发明人： Chu Yun Fu ,  Chia Shiung Tsai ,  Syun-Ming Jang

IPC分类号： H01L214763

CPC分类号： H01L21/76829 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/76801 ,  H01L21/7681 ,  H01L21/76813

摘要： The present invention provides an anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer and two compatible oxide etch processes. The Si-Rich Silicon oxynitride (SiON) etch barrier layer can be used as a hard mask in a dual damascene structure and as a hard mask for over a polysilicone gate. The invention has the following key elements: 1) Si rich Silicon oxynitride (SiON) ARC layer, 2) Special Silicon oxide Etch process that has a high selectivity of Si-Rich SiON to silicon oxide or SiN; 3) Special Si Rich SiON spacer process for a self aligned contact (SAC). A dual damascene structure is formed by depositing a first dielectric layer. A novel anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer is deposited on top of the first dielectric layer. A first opening is etched in the first insulating layer. A second dielectric layer is deposited on the anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer. A second dual damascene opening is etched into the dielectric layers. The anti-reflective Si-Rich Silicon oxynnitride (SiON) etch barrier layer can also serve as an ARC layer during these operations to reduce the amount of reflectance from conductive region to reduce distortion of the photoresist pattern.

摘要翻译： 本发明提供了抗反射富Si硅氮化硅（SiON）蚀刻阻挡层和两种相容的氧化物蚀刻工艺。 Si富氧硅氮化物（SiON）蚀刻阻挡层可用作双镶嵌结构中的硬掩模，并且可用作多晶硅栅极上的硬掩模。 本发明具有以下关键要素：1）富硅氧氮化硅（SiON）ARC层，2）具有Si富Si硅对硅氧化物或SiN的高选择性的特殊氧化硅蚀刻工艺; 3）用于自对准接触（SAC）的特殊Si Rich SiON隔离工艺。通过沉积第一介电层形成双镶嵌结构。 在第一介电层的顶部沉积有新的抗反射硅富氮硅氮化硅（SiON）蚀刻阻挡层。 在第一绝缘层中蚀刻第一开口。 第二电介质层沉积在抗反射富Si硅氮化硅（SiON）蚀刻阻挡层上。 第二个双镶嵌开口被蚀刻到电介质层中。 在这些操作期间，抗反射Si富硅氧氮化物（SiON）蚀刻阻挡层也可以用作ARC层，以减少来自导电区域的反射率，以减少光致抗蚀剂图案的变形。

公开(公告)号：US06245669B1

公开(公告)日：2001-06-12

申请号：US09245564

申请日：1999-02-05

申请人： Chu Yun Fu ,  Chia Shiung Tsai ,  Syun-Ming Jang

发明人： Chu Yun Fu ,  Chia Shiung Tsai ,  Syun-Ming Jang

IPC分类号： H01L214763

CPC分类号： H01L21/76829 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/76801 ,  H01L21/7681 ,  H01L21/76813

摘要： The present invention provides an anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer and two compatible oxide etch processes. The Si-Rich Silicon oxynitride (SiON) etch barrier layer can be used as a hard mask in a dual damascene structure and as a hard mask for over a polysilicon gate. The invention has the following key elements: 1) Si rich Silicon oxynitride (SiON) ARC layer, 2) Special Silicon oxide Etch process that has a high selectivity of Si-Rich SiON to silicon oxide or SiN; 3) Special Si Rich SiON spacer process for a self aligned contact (SAC). A dual damascene structure is formed by depositing a first dielectric layer. A novel anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer is deposited on top of the first dielectric layer. A first opening is etched in the first insulating layer. A second dielectric layer is deposited on the anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer. A second dual damascene opening is etched into the dielectric layers. The anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer can also serve as an ARC layer during these operations to reduce the amount of reflectance from conductive region to reduce distortion of the photoresist pattern.

摘要翻译： 本发明提供了抗反射富Si硅氮化硅（SiON）蚀刻阻挡层和两种相容的氧化物蚀刻工艺。 Si富氧硅氮化物（SiON）蚀刻阻挡层可用作双镶嵌结构中的硬掩模，并可用作多晶硅栅极上的硬掩模。 本发明具有以下关键要素：1）富硅氧氮化硅（SiON）ARC层，2）具有Si富Si硅对硅氧化物或SiN的高选择性的特殊氧化硅蚀刻工艺; 3）用于自对准接触（SAC）的特殊Si Rich SiON隔离工艺。通过沉积第一介电层形成双镶嵌结构。 在第一介电层的顶部沉积有新的抗反射硅富氮硅氮化硅（SiON）蚀刻阻挡层。 在第一绝缘层中蚀刻第一开口。 第二电介质层沉积在抗反射富Si硅氮化硅（SiON）蚀刻阻挡层上。 第二个双镶嵌开口被蚀刻到电介质层中。 在这些操作期间，抗反射硅富氮硅氮化物（SiON）蚀刻阻挡层也可以用作ARC层，以减少来自导电区域的反射率，以减少光致抗蚀剂图案的失真。