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    MULTI-STRAINED SOURCE/DRAIN STRUCTURES
    5.
    发明申请
    MULTI-STRAINED SOURCE/DRAIN STRUCTURES 有权
    多应变源/排水结构

    公开(公告)号：US20110291201A1

    公开(公告)日：2011-12-01

    申请号：US12787972

    申请日：2010-05-26

    申请人： Chun-Fai Cheng ,  Fung Ka Hing ,  Ming-Huan Tsai ,  Chun-Feng Nieh ,  Yimin Huang ,  Han-Ting Tsai ,  Haiting Wang

    发明人： Chun-Fai Cheng ,  Fung Ka Hing ,  Ming-Huan Tsai ,  Chun-Feng Nieh ,  Yimin Huang ,  Han-Ting Tsai ,  Haiting Wang

    IPC分类号： H01L27/088 ,  H01L21/8234

    CPC分类号： H01L29/7848 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/30608 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

    摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a silicon substrate. The semiconductor device includes first and second regions that are disposed in the substrate. The first and second regions have a silicon compound material. The semiconductor device includes first and second source/drain structures that are partially disposed in the first and second regions, respectively. The semiconductor device includes a first gate that is disposed over the substrate. The first gate has a first proximity to the first region. The semiconductor device includes a second gate that is disposed over the substrate. The second gate has a second proximity to the second region. The second proximity is different from the first proximity. The first source/drain structure and the first gate are portions of a first transistor, and the second source/drain structure and the second gate are portions of a second transistor.

    摘要翻译： 本发明提供一种半导体器件。 半导体器件包括硅衬底。 半导体器件包括设置在衬底中的第一和第二区域。 第一和第二区域具有硅化合物材料。 半导体器件包括分别部分地设置在第一和第二区域中的第一和第二源/漏结构。 半导体器件包括设置在衬底上的第一栅极。 第一个门第一个靠近第一个地区。 半导体器件包括设置在衬底上的第二栅极。 第二个门第二个靠近第二个区域。 第二接近度不同于第一接近度。 第一源极/漏极结构和第一栅极是第一晶体管的部分，并且第二源极/漏极结构和第二栅极是第二晶体管的部分。

    Contact or via hole structure with enlarged bottom critical dimension
    6.
    发明授权
    Contact or via hole structure with enlarged bottom critical dimension 有权
    接触或通孔结构，扩大底部临界尺寸

    公开(公告)号：US07511349B2

    公开(公告)日：2009-03-31

    申请号：US11207450

    申请日：2005-08-19

    申请人： Ming-Huan Tsai ,  Fang-Cheng Chen ,  Chao-Cheng Chen ,  Syun-Ming Jang

    发明人： Ming-Huan Tsai ,  Fang-Cheng Chen ,  Chao-Cheng Chen ,  Syun-Ming Jang

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L21/76897 ,  H01L21/76804 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit chip includes a buffer layer, an underlying layer, a dielectric layer, a hole, and barrier layer. The buffer layer is over the underlying layer. The dielectric layer is over the buffer layer. The hole is formed in and extending through the dielectric layer and the buffer layer, and opens to the underlying layer. The hole includes a buffer layer portion at the buffer layer and a dielectric layer portion at the dielectric layer. At least part of the buffer layer portion of the hole has a larger cross-section area than a smallest cross-section area of the dielectric layer portion of the hole. The conformal barrier layer covers surfaces of the dielectric layer and the buffer layer in the hole. The hole is a via hole or a contact hole that is later filled with a conductive material to form a conductive via or a conductive contact.

    摘要翻译： 集成电路芯片包括缓冲层，下层，电介质层，空穴和阻挡层。 缓冲层位于底层之上。 电介质层在缓冲层之上。 孔形成并延伸穿过介电层和缓冲层，并向下层开放。 该孔包括在缓冲层处的缓冲层部分和介电层处的电介质层部分。 孔的缓冲层部分的至少一部分具有比孔的电介质层部分的最小横截面面积更大的横截面面积。 保形阻挡层覆盖孔中的介电层和缓冲层的表面。 孔是通孔或接触孔，其后面填充有导电材料以形成导电通孔或导电接触。

    Novel gate structure and method of forming the gate dielectric with mini-spacer
    7.
    发明申请
    Novel gate structure and method of forming the gate dielectric with mini-spacer 审中-公开
    具有微型间隔物形成栅极电介质的新型栅极结构和方法

    公开(公告)号：US20050127459A1

    公开(公告)日：2005-06-16

    申请号：US11048205

    申请日：2005-02-01

    申请人： Yuan-Hung Chiu ,  Ming-Huan Tsai ,  Fang-Cheng Chen ,  Hun-Jan Tao

    发明人： Yuan-Hung Chiu ,  Ming-Huan Tsai ,  Fang-Cheng Chen ,  Hun-Jan Tao

    IPC分类号： H01L21/265 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/80

    CPC分类号： H01L21/2652 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

    摘要： A field effect transistor gate structure and a method of fabricating the gate structure with a high-k gate dielectric material and high-k spacer are described. A gate pattern or trench is first etched in a dummy organic or inorganic film deposited over a silicon substrate with source/drain regions. A high-k dielectric material liner is then deposited on all exposed surfaces. Excess poly-silicon gate conductor film is then deposited within and over the trench to provide adequate overburden. Poly-silicon is then planarized with chemical mechanical polishing or etch-back methods such that the high-k material film on top of the dummy film surface is removed during this step. In the final step, the dummy film is disposed off, leaving the final transistor gate structure with high-k gate dielectric and high-k spacer surrounding the gate conductor poly-silicon, with the entire gate structure fabricated to form an FET device on a silicon substrate.

    摘要翻译： 描述了场效应晶体管栅极结构和制造具有高k栅极介电材料和高k隔离物的栅极结构的方法。 首先在具有源极/漏极区域的硅衬底上沉积的虚拟有机或无机膜中蚀刻栅极图案或沟槽。 然后将高k电介质材料衬垫沉积在所有暴露的表面上。 然后将过多的多晶硅栅极导体膜沉积在沟槽内和沟槽上，以提供足够的覆盖层。 然后通过化学机械抛光或蚀刻方法对多晶硅进行平面化，使得在该步骤期间去除虚拟膜表面顶部的高k材料膜。 在最后的步骤中，将虚设薄膜放开，留下最终的晶体管栅极结构，其中高k栅极电介质和围绕栅极导体多晶硅的高k隔离层，整个栅极结构被制成以形成FET器件 硅衬底。

    Metal silicide etch resistant plasma etch method
    9.
    发明授权
    Metal silicide etch resistant plasma etch method 失效
    金属硅化物抗蚀刻等离子体蚀刻方法

    公开(公告)号：US06706640B1

    公开(公告)日：2004-03-16

    申请号：US10292355

    申请日：2002-11-12

    申请人： Ming-Huan Tsai ,  Ju-Wang Hsu ,  Peng-Fu Hsu ,  Hun-Jan Tao

    发明人： Ming-Huan Tsai ,  Ju-Wang Hsu ,  Peng-Fu Hsu ,  Hun-Jan Tao

    IPC分类号： H01L21302

    CPC分类号： H01L21/28518 ,  H01L21/31116 ,  H01L21/76802

    摘要： A plasma etch method for etching a dielectric layer and an etch stop layer to reach a metal silicide layer formed thereunder employs for etching the etch stop layer an etchant gas composition comprising a fluorine containing gas and a nitrogen containing gas, preferably with a carrier gas such as argon or helium, but without an oxygen containing gas or a carbon and oxygen containing gas. The plasma etch method is selective for the etch stop layer with respect to the metal silicide layer, thus maintaining the physical and electrical integrity of the metal silicide layer.

    摘要翻译： 用于蚀刻介电层和蚀刻停止层以达到其下形成的金属硅化物层的等离子体蚀刻方法用于蚀刻蚀刻停止层包括含氟气体和含氮气体的蚀刻剂气体组合物，优选地使用载气如 作为氩或氦，但不含含氧气体或含碳和氧的气体。 等离子体蚀刻方法对于蚀刻停止层相对于金属硅化物层是选择性的，从而保持金属硅化物层的物理和电气完整性。

    Selectivity oxide-to-oxynitride etch process using a fluorine containing gas, an inert gas and a weak oxidant
    10.
    发明授权
    Selectivity oxide-to-oxynitride etch process using a fluorine containing gas, an inert gas and a weak oxidant 有权
    使用含氟气体，惰性气体和弱氧化剂的选择性氧化物 - 氧氮化物蚀刻工艺

    公开(公告)号：US06436841B1

    公开(公告)日：2002-08-20

    申请号：US09949506

    申请日：2001-09-10

    申请人： Ming Huan Tsai ,  Bao-Ching Pen ,  Mei-Ru Kuo ,  Hun-Jan Tao

    发明人： Ming Huan Tsai ,  Bao-Ching Pen ,  Mei-Ru Kuo ,  Hun-Jan Tao

    IPC分类号： H01L21302

    CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L21/3144

    摘要： A method of forming a borderless contact, comprising the following steps. A substrate having an exposed conductive structure is provided. An oxynitride etch stop layer is formed over the substrate and the exposed conductive structure. An oxide dielectric layer is formed over the oxynitride etch stop layer. The oxide dielectric layer is etched with an etch process having a high selectivity of oxide-to-oxynitride to form a contact hole therein exposing a portion of the oxynitride etch stop layer over at least a portion of the exposed conductive structure. The etch process not appreciably etching the oxynitride etch stop layer and including: a fluorine containing gas; an inert gas; and a weak oxidant. The exposed portion of the oxynitride etch stop layer over at least a portion of the conductive structure is removed. A borderless contact is formed within the contact hole. The borderless contact being in electrical connection with at least a portion of the conductive structure.

    摘要翻译： 一种形成无边界接触的方法，包括以下步骤。 提供具有暴露的导电结构的衬底。 在衬底和暴露的导电结构之上形成氮氧化物蚀刻停止层。 在氧氮化物蚀刻停止层上形成氧化物介电层。 用具有高选择性的氧化物 - 氮氧化物的蚀刻工艺来蚀刻氧化物介电层，以在其中形成接触孔，使暴露的导电结构的至少一部分上的氮氧化物蚀刻停止层的一部分暴露。 蚀刻工艺不明显地蚀刻氧氮化物蚀刻停止层，并且包括：含氟气体; 惰性气体 和弱氧化剂。 除去导电结构的至少一部分上的氧氮化物蚀刻停止层的暴露部分。 在接触孔内形成无边界接触。 无边界接触与至少一部分导电结构电连接。