公开(公告)号：US20110013326A1

公开(公告)日：2011-01-20

申请号：US12891474

申请日：2010-09-27

申请人： Ming-Dou Ker ,  Shih-Hung Chen ,  Kun-Hsien Lin

发明人： Ming-Dou Ker ,  Shih-Hung Chen ,  Kun-Hsien Lin

IPC分类号： H02H9/04 ,  H01L27/06

CPC分类号： H01L23/62 ,  H01L27/0262 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device for electrostatic discharge (ESD) protection comprises a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor.

摘要翻译： 一种用于静电放电（ESD）保护的半导体器件包括可控硅整流器（SCR），其包括半导体衬底，形成在衬底中的第一阱，在衬底中形成的第二阱，形成在第一阱中的第一p型区 用作阳极，以及部分地形成在第二阱中用作阴极的第一n型区域，形成在包括栅极的第一阱中的p型金属氧化物半导体（PMOS）晶体管，第一扩散层 区域和与第一扩散区域分离的第二扩散区域，形成在电连接到PMOS晶体管的第一扩散区域的第一阱中的第二n型区域和形成在衬底中的第二p型区域电连接 到PMOS晶体管的第二扩散区域。

公开(公告)号：US20050270710A1

公开(公告)日：2005-12-08

申请号：US10857836

申请日：2004-06-02

申请人： Ming-Dou Ker ,  Kun-Hsien Lin

发明人： Ming-Dou Ker ,  Kun-Hsien Lin

IPC分类号： H01L27/02 ,  H01L29/74 ,  H02H9/00

CPC分类号： H01L27/0262 ,  H01L29/7436

摘要： The present invention relates to an SCR (Silicon Controlled Rectifier) for the ESD (electrostatic discharge) protection comprising two terminal electrodes of a first electrode and a second electrode, a PMOS, an NMOS and an SCR structure. By utilizing an embedded SCR, a whole-chip ESD protection circuit design can be obtained. The present invention is suitable for IC products, and for applications by IC design industries and IC foundry industries.

摘要翻译： 本发明涉及一种用于ESD（静电放电）保护的SCR（硅控整流器），其包括第一电极和第二电极，PMOS，NMOS和SCR结构的两个端电极。 通过利用嵌入式SCR，可以获得全芯片ESD保护电路设计。 本发明适用于IC产品，适用于IC设计行业和IC铸造行业。

公开(公告)号：US07825473B2

公开(公告)日：2010-11-02

申请号：US11186086

申请日：2005-07-21

申请人： Ming-Dou Ker ,  Shih-Hung Chen ,  Kun-Hsien Lin

发明人： Ming-Dou Ker ,  Shih-Hung Chen ,  Kun-Hsien Lin

IPC分类号： H01L23/62

CPC分类号： H01L23/62 ,  H01L27/0262 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device for electrostatic discharge (ESD) protection comprises a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor.

摘要翻译： 一种用于静电放电（ESD）保护的半导体器件包括可控硅整流器（SCR），其包括半导体衬底，形成在衬底中的第一阱，在衬底中形成的第二阱，形成在第一阱中的第一p型区 用作阳极，以及部分地形成在第二阱中用作阴极的第一n型区域，形成在包括栅极的第一阱中的p型金属氧化物半导体（PMOS）晶体管，第一扩散层 区域和与第一扩散区域分离的第二扩散区域，形成在电连接到PMOS晶体管的第一扩散区域的第一阱中的第二n型区域和形成在衬底中的第二p型区域电连接 到PMOS晶体管的第二扩散区域。

公开(公告)号：US08102001B2

公开(公告)日：2012-01-24

申请号：US12891474

申请日：2010-09-27

申请人： Ming-Dou Ker ,  Shih-Hung Chen ,  Kun-Hsien Lin

发明人： Ming-Dou Ker ,  Shih-Hung Chen ,  Kun-Hsien Lin

IPC分类号： H01L23/62

CPC分类号： H01L23/62 ,  H01L27/0262 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device for electrostatic discharge (ESD) protection includes a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor.

摘要翻译： 一种用于静电放电（ESD）保护的半导体器件包括可控硅整流器（SCR），其包括半导体衬底，形成在衬底中的第一阱，形成在衬底中的第二阱，形成在第一阱中的第一p型区 用作阳极，以及部分地形成在第二阱中用作阴极的第一n型区域，形成在包括栅极的第一阱中的p型金属氧化物半导体（PMOS）晶体管，第一扩散层 区域和与第一扩散区域分离的第二扩散区域，形成在电连接到PMOS晶体管的第一扩散区域的第一阱中的第二n型区域和形成在衬底中的第二p型区域电连接 到PMOS晶体管的第二扩散区域。

公开(公告)号：US20070018193A1

公开(公告)日：2007-01-25

申请号：US11186086

申请日：2005-07-21

申请人： Ming-Dou Ker ,  Shih-Hung Chen ,  Kun-Hsien Lin

发明人： Ming-Dou Ker ,  Shih-Hung Chen ,  Kun-Hsien Lin

IPC分类号： H01L29/417

CPC分类号： H01L23/62 ,  H01L27/0262 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device for electrostatic discharge (ESD) protection comprises a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor.

摘要翻译： 一种用于静电放电（ESD）保护的半导体器件包括可控硅整流器（SCR），其包括半导体衬底，形成在衬底中的第一阱，在衬底中形成的第二阱，形成在第一阱中的第一p型区 用作阳极，以及部分地形成在第二阱中用作阴极的第一n型区域，形成在包括栅极的第一阱中的p型金属氧化物半导体（PMOS）晶体管，第一扩散层 区域和与第一扩散区域分离的第二扩散区域，形成在电连接到PMOS晶体管的第一扩散区域的第一阱中的第二n型区域和形成在衬底中的第二p型区域电连接 到PMOS晶体管的第二扩散区域。

公开(公告)号：US07129546B2

公开(公告)日：2006-10-31

申请号：US10992362

申请日：2004-11-19

申请人： Ming-Dou Ker ,  Kun-Hsien Lin ,  Geeng-Lih Lin

发明人： Ming-Dou Ker ,  Kun-Hsien Lin ,  Geeng-Lih Lin

IPC分类号： H01L23/62

CPC分类号： H01L27/0266 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/41725 ,  H01L29/7835

摘要： An ESD protection device. The ESD protection device has a substrate; a channel region, a source region, and a drain region. The channel region is formed on a predetermined area of a surface of the substrate, the channel region has a first side and a second side. The source region is formed adjacent to the first side. The drain region which has a heavily doped region and a lightly doped region formed below the heavily doped region is formed adjacent to the second side. The width along a longitudinal axis of the heavily doped region has variable length and thus the length between one side of the heavily doped region to the second side has variable length.

摘要翻译： ESD保护装置。 ESD保护装置具有基板; 沟道区，源极区和漏极区。 沟道区形成在基板的表面的预定区域上，沟道区具有第一面和第二面。 源区域与第一侧相邻地形成。 具有重掺杂区域和形成在重掺杂区域下方的轻掺杂区域的漏区形成为与第二侧相邻。 沿着重掺杂区域的纵轴的宽度具有可变长度，因此重掺杂区域的一侧与第二侧之间的长度具有可变长度。

公开(公告)号：US07098511B2

公开(公告)日：2006-08-29

申请号：US10973264

申请日：2004-10-27

申请人： Ming-Dou Ker ,  Kun-Hsien Lin

发明人： Ming-Dou Ker ,  Kun-Hsien Lin

IPC分类号： H01L23/62

CPC分类号： H01L27/0292 ,  H01L27/0251

摘要： The claimed invention discloses an ESD protection circuit that is applied to an IC with power-down-mode operation. When the IC goes into power-down-mode operation, leakage current and charging from the I/O pad to the VDD power line could be prevented by applying the present invention. Therefore, the malfunction of the IC can be avoided. There still have two ESD clamp circuits respectively connected between the VDD power line and the VSS power line and between ESD bus line and VSS power line, so as to achieve the whole chip ESD protection scheme. The present invention can prevent ESD protection circuit from resulting in leakage current or malfunction under power-down-mode operation, and moreover achieve whole chip ESD protection scheme.

摘要翻译： 所要求保护的发明公开了一种ESD保护电路，其被应用于具有掉电模式操作的IC。 当IC进入掉电模式操作时，可以通过应用本发明来防止漏电流和从I / O焊盘到VDD电源线的充电。 因此，可以避免IC的故障。 在VDD电源线和VSS电源线之间以及ESD总线与VSS电源线之间分别连接有两个ESD钳位电路，从而实现了整个芯片的ESD保护方案。 本发明可以防止ESD保护电路在掉电模式下产生漏电流或故障，而且可实现全芯片ESD保护方案。

公开(公告)号：US20050174707A1

公开(公告)日：2005-08-11

申请号：US10973264

申请日：2004-10-27

申请人： Ming-Dou Ker ,  Kun-Hsien Lin

发明人： Ming-Dou Ker ,  Kun-Hsien Lin

IPC分类号： H01L23/60 ,  H01L23/62 ,  H01L27/02 ,  H02H9/00

CPC分类号： H01L27/0292 ,  H01L27/0251

摘要： The claimed invention discloses an ESD protection circuit that is applied to an IC with power-down-mode operation. When the IC goes into power-down-mode operation, leakage current and charging from the I/O pad to the VDD power line could be prevented by applying the present invention. Therefore, the malfunction of the IC can be avoided. There still have two ESD clamp circuits respectively connected between the VDD power line and the VSS power line and between ESD bus line and VSS power line, so as to achieve the whole chip ESD protection scheme. The present invention can prevent ESD protection circuit from resulting in leakage current or malfunction under power-down-mode operation, and moreover achieve whole chip ESD protection scheme.

摘要翻译： 所要求保护的发明公开了一种ESD保护电路，其被应用于具有掉电模式操作的IC。 当IC进入掉电模式操作时，可以通过应用本发明来防止漏电流和从I / O焊盘到VDD电源线的充电。 因此，可以避免IC的故障。 在VDD电源线和VSS电源线之间以及ESD总线与VSS电源线之间分别连接有两个ESD钳位电路，从而实现了整个芯片的ESD保护方案。 本发明可以防止ESD保护电路在掉电模式下产生漏电流或故障，而且可实现全芯片ESD保护方案。

公开(公告)号：US20050122645A1

公开(公告)日：2005-06-09

申请号：US10726641

申请日：2003-12-04

申请人： Ming-Dou Ker ,  Kun-Hsien Lin

发明人： Ming-Dou Ker ,  Kun-Hsien Lin

IPC分类号： H05K1/02 ,  H05K1/11 ,  H05K9/00 ,  H02H9/00

CPC分类号： H05K1/0259 ,  H05K1/117 ,  H05K9/0067 ,  H05K2201/09354 ,  H05K2201/094 ,  H05K2201/10689

摘要： An interface device coupled to a board on which integrated circuits are mounted for providing electrostatic discharge protection for the integrated circuits that comprises a plurality of first contact members, each of the first contact members including one end connected to the board and the other end to connect to an external device, and at least one second contact member connected to a voltage line of a voltage level, wherein the at least one second contact member includes a length greater than that of each of the first contact members.

摘要翻译： 一种接口装置，其耦合到其上安装有集成电路的板，用于为包括多个第一接触构件的集成电路提供静电放电保护，所述第一接触构件中的每一个包括连接到所述板的一端和用于连接的另一端 连接到电压电平的电压线的至少一个第二接触构件，其中所述至少一个第二接触构件的长度大于每个所述第一接触构件的长度。

公开(公告)号：US06867461B1

公开(公告)日：2005-03-15

申请号：US10814128

申请日：2004-04-01

申请人： Ming-Dou Ker ,  Kun-Hsien Lin

发明人： Ming-Dou Ker ,  Kun-Hsien Lin

IPC分类号： H01L23/60 ,  H01L23/62 ,  H01L27/02 ,  H02H9/00

CPC分类号： H01L27/0292 ,  H01L27/0251

摘要： The claimed invention discloses an ESD protection circuit that is applied to an IC with power-down-mode operation. When the IC goes into power-down-mode operation, leakage current and charging from the I/O pad to the VDD power line could be prevented by applying the present invention. Therefore, the malfunction of the IC can be avoided. There still have two ESD clamp circuits respectively connected between the VDD power line and the VSS power line and between ESD bus line and VSS power line, so as to achieve the whole chip ESD protection scheme. The present invention can prevent ESD protection circuit from resulting in leakage current or malfunction under power-down-mode operation, and moreover achieve whole chip ESD protection scheme.