公开(公告)号：US20110076832A1

公开(公告)日：2011-03-31

申请号：US12570926

申请日：2009-09-30

申请人： Ming-Jie HUANG ,  Chen-Ping CHEN ,  Tung-Ying LEE

发明人： Ming-Jie HUANG ,  Chen-Ping CHEN ,  Tung-Ying LEE

IPC分类号： H01L21/762 ,  H01L21/302

CPC分类号： H01L21/76232 ,  H01L21/3081

摘要： A method of forming a hardmask for defining shallow trench isolation regions in a semiconductor substrate layer includes the steps of: depositing a hardmask layer over the semiconductor substrate layer; depositing and patterning a first photoresist layer over the hardmask layer; etching the hardmask layer after patterning the first photoresist layer to form an interim hardmask layer having at least one line feature; depositing and patterning a second photoresist layer over the interim hardmask layer; and forming a hardmask, the forming step including etching the interim hardmask layer after patterning the second photoresist layer to define a line end of the at least one line feature.

摘要翻译： 在半导体衬底层中形成用于限定浅沟槽隔离区的硬掩模的方法包括以下步骤：在半导体衬底层上沉积硬掩模层; 在硬掩模层上沉积和图案化第一光致抗蚀剂层; 在图案化第一光致抗蚀剂层之后蚀刻硬掩模层以形成具有至少一个线特征的临时硬掩模层; 在所述临时硬掩模层上沉积和图案化第二光致抗蚀剂层; 以及形成硬掩模，所述形成步骤包括在图案化所述第二光致抗蚀剂层之后蚀刻所述临时硬掩模层以限定所述至少一个线特征的线端。

公开(公告)号：US20120021607A1

公开(公告)日：2012-01-26

申请号：US12842162

申请日：2010-07-23

申请人： Ming-Jie HUANG ,  Chen-Ping CHEN

发明人： Ming-Jie HUANG ,  Chen-Ping CHEN

IPC分类号： H01L21/311 ,  H01L21/31

CPC分类号： H01L21/32139 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144

摘要： An embodiment of the disclosure includes a method of pitch reduction. A substrate is provided. A first material layer is formed over the substrate. A second material layer is formed on the first material layer. A hardmask layer is formed on the second material layer. A first imaging layer is formed on the hardmask layer. The first imaging layer is patterned to form a plurality of first features over the hardmask layer. The hardmask layer is etched utilizing the first imaging layer as a mask to form the first features in the hardmask layer. The first imaging layer is removed to expose the etched hardmask layer and a portion of a top surface of the second material layer. A second imaging layer is formed and the process is repeated, such that first and second features are alternating with a pitch substantially half the original pitch.

摘要翻译： 本公开的一个实施例包括减小音调的方法。 提供基板。 第一材料层形成在衬底上。 在第一材料层上形成第二材料层。 硬掩模层形成在第二材料层上。 第一成像层形成在硬掩模层上。 图案化第一成像层以在硬掩模层上形成多个第一特征。 使用第一成像层作为掩模蚀刻硬掩模层以形成硬掩模层中的第一特征。 去除第一成像层以暴露蚀刻的硬掩模层和第二材料层的顶表面的一部分。 形成第二成像层并且重复该过程，使得第一和第二特征以基本上相当于原始间距的一半的间距交替。

公开(公告)号：US20120018786A1

公开(公告)日：2012-01-26

申请号：US13251961

申请日：2011-10-03

申请人： Ta-Wei KAO ,  Shiang-Bau WANG ,  Ming-Jie HUANG ,  Chi-Hsi WU ,  Shu-Yuan KU

发明人： Ta-Wei KAO ,  Shiang-Bau WANG ,  Ming-Jie HUANG ,  Chi-Hsi WU ,  Shu-Yuan KU

IPC分类号： H01L29/78

CPC分类号： H01L29/78 ,  H01L29/66636

摘要： A semiconductor device is formed by a multi-step etching process that produces trench openings in a silicon substrate immediately adjacent transistor gate structures formed over the substrate surface. The multi-step etching process is a Br-based etching operation with one step including nitrogen and a further step deficient of nitrogen. The etching process does not attack the transistor structure and forms the openings. The openings are bounded by upper surfaces that extend downwardly from the substrate surface and are substantially vertical, and lower surfaces that bulge outwardly from the upper vertical sections and undercut the transistor structure. The openings may be filled with a suitable source/drain material to produce SSD transistors with desirable Idsat characteristics.

摘要翻译： 通过多步骤蚀刻工艺形成半导体器件，该工艺在与衬底表面上形成的晶体管栅极结构紧邻的硅衬底中产生沟槽开口。 多步骤蚀刻工艺是基于Br的蚀刻操作，其中一步包括氮气和另一个缺陷氮气。 蚀刻工艺不会影响晶体管结构并形成开口。 开口由从基板表面向下延伸并且基本上垂直的上表面和从上垂直部分向外凸出并下切晶体管结构的下表面限定。 可以用合适的源极/漏极材料填充开口以产生具有期望的Idsat特性的SSD晶体管。

公开(公告)号：US20120100681A1

公开(公告)日：2012-04-26

申请号：US12981610

申请日：2010-12-30

申请人： Ziwei FANG ,  Jeff J. XU ,  Ming-Jie HUANG ,  Yimin HUANG ,  Zhiqiang WU ,  Min CAO

发明人： Ziwei FANG ,  Jeff J. XU ,  Ming-Jie HUANG ,  Yimin HUANG ,  Zhiqiang WU ,  Min CAO

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/02057 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/30604 ,  H01L21/30608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78

摘要： An integrated circuit device and method for manufacturing the integrated circuit device provide improved control over a shape of a trench for forming the source and drain features of integrated circuit device, by forming a second doped region in a first doped region and removing the first and the second doped regions by a first and a second wet etching processes.

摘要翻译： 用于制造集成电路器件的集成电路器件和方法通过在第一掺杂区域中形成第二掺杂区域并且去除第一和第二掺杂区域，从而提供对用于形成集成电路器件的源极和漏极特征的沟槽形状的改进的控制 第二掺杂区域通过第一和第二湿蚀刻工艺。

公开(公告)号：US20100270598A1

公开(公告)日：2010-10-28

申请号：US12428905

申请日：2009-04-23

申请人： Ta-Wei KAO ,  Shiang-Bau WANG ,  Ming-Jie HUANG ,  Chi-Hsi WU ,  Shu-Yuan KU

发明人： Ta-Wei KAO ,  Shiang-Bau WANG ,  Ming-Jie HUANG ,  Chi-Hsi WU ,  Shu-Yuan KU

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/78 ,  H01L29/66636

摘要： A multi-step etching process produces trench openings in a silicon substrate that are immediately adjacent transistor structures formed over the substrate surface. The multi-step etching process is a Br-based etching operation with one step including nitrogen and a further step deficient of nitrogen. The etching process does not attack the transistor structure and forms an opening bounded by upper surfaces that extend downwardly from the substrate surface and are substantially vertical, and lower surfaces that bulge outwardly from the upper vertical sections and undercut the transistor structure. The aggressive undercut produces a desirable stress in the etched silicon surface. The openings are then filled with a suitable source/drain material and SSD transistors with desirable Idsat characteristics may then be formed.

摘要翻译： 多步骤蚀刻工艺在硅衬底中产生与衬底表面上形成的立即相邻的晶体管结构的沟槽开口。 多步骤蚀刻工艺是基于Br的蚀刻操作，其中一步包括氮气和另一个缺陷氮气。 蚀刻工艺不会对晶体管结构产生冲击，并形成由从衬底表面向下延伸并且基本上垂直的上表面限定的开口，以及从上垂直部分向外凸出并切割晶体管结构的下表面。 侵蚀性底切在蚀刻的硅表面产生理想的应力。 然后用合适的源极/漏极材料填充开口，然后可以形成具有期望的Idsat特性的SSD晶体管。