公开(公告)号：US20060205224A1

公开(公告)日：2006-09-14

申请号：US11318934

申请日：2005-12-27

申请人： Ming-Jie Huang ,  Shu-Chih Yang ,  Huan-Just Lin ,  Yung-Tin Chen ,  Hun-Jan Tao

发明人： Ming-Jie Huang ,  Shu-Chih Yang ,  Huan-Just Lin ,  Yung-Tin Chen ,  Hun-Jan Tao

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/32139 ,  H01L21/28123

摘要： Large-scale trimming for forming ultra-narrow gates for semiconductor devices is disclosed. A hard mask layer on a semiconductor wafer below a patterned soft mask layer on the semiconductor wafer is etched to narrow a width of the hard mask layer. The hard mask layer is trimmed to further narrow the width of the hard mask layer, where the soft mask layer has been removed. At least a gate electrode layer below the hard mask layer on the semiconductor wafer is etched, resulting in the gate electrode layer having a width substantially identical to the width of the hard mask layer as trimmed. The gate electrode layer as etched forms the ultra-narrow gate electrode on the semiconductor wafer, where the hard mask layer has been removed.

公开(公告)号：US20050133827A1

公开(公告)日：2005-06-23

申请号：US10738239

申请日：2003-12-17

申请人： Ming-Jie Huang ,  Shu-Chih Yang ,  Huan-Just Lin ,  Yung-Tin Chen ,  Hun-Jan Tao

发明人： Ming-Jie Huang ,  Shu-Chih Yang ,  Huan-Just Lin ,  Yung-Tin Chen ,  Hun-Jan Tao

IPC分类号： H01L21/28 ,  H01L21/3213 ,  H01L29/745

CPC分类号： H01L21/32139 ,  H01L21/28123

摘要： Large-scale trimming for forming ultra-narrow gates for semiconductor devices is disclosed. A hard mask layer on a semiconductor wafer below a patterned soft mask layer on the semiconductor wafer is etched to narrow a width of the hard mask layer. The hard mask layer is trimmed to further narrow the width of the hard mask layer, where the soft mask layer has been removed. At least a gate electrode layer below the hard mask layer on the semiconductor wafer is etched, resulting in the gate electrode layer having a width substantially identical to the width of the hard mask layer as trimmed. The gate electrode layer as etched forms the ultra-narrow gate electrode on the semiconductor wafer, where the hard mask layer has been removed.

摘要翻译： 公开了用于形成用于半导体器件的超窄栅极的大规模修整。 蚀刻在半导体晶片上的图案化软掩模层下方的半导体晶片上的硬掩模层，以使硬掩模层的宽度变窄。 修剪硬掩模层以进一步缩小已经去除软掩模层的硬掩模层的宽度。 蚀刻半导体晶片上的硬掩模层下方的至少栅极电极层，导致栅极电极层的宽度与被修整的硬掩模层的宽度基本相同。 蚀刻的栅极电极层形成半导体晶片上的超窄栅电极，其中硬掩模层被去除。

公开(公告)号：US07008866B2

公开(公告)日：2006-03-07

申请号：US10738239

申请日：2003-12-17

申请人： Ming-Jie Huang ,  Shu-Chih Yang ,  Huan-Just Lin ,  Yung-Tin Chen ,  Hun-Jan Tao

发明人： Ming-Jie Huang ,  Shu-Chih Yang ,  Huan-Just Lin ,  Yung-Tin Chen ,  Hun-Jan Tao

IPC分类号： H01L21/3205

CPC分类号： H01L21/32139 ,  H01L21/28123

摘要： Large-scale trimming for forming ultra-narrow gates for semiconductor devices is disclosed. A hard mask layer on a semiconductor wafer below a patterned soft mask layer on the semiconductor wafer is etched to narrow a width of the hard mask layer. The hard mask layer is trimmed to further narrow the width of the hard mask layer, where the soft mask layer has been removed. At least a gate electrode layer below the hard mask layer on the semiconductor wafer is etched, resulting in the gate electrode layer having a width substantially identical to the width of the hard mask layer as trimmed. The gate electrode layer as etched forms the ultra-narrow gate electrode on the semiconductor wafer, where the hard mask layer has been removed.

摘要翻译： 公开了用于形成用于半导体器件的超窄栅极的大规模修整。 蚀刻在半导体晶片上的图案化软掩模层下方的半导体晶片上的硬掩模层，以使硬掩模层的宽度变窄。 修剪硬掩模层以进一步缩小已经去除软掩模层的硬掩模层的宽度。 蚀刻半导体晶片上的硬掩模层下方的至少栅极电极层，导致栅极电极层的宽度与被修整的硬掩模层的宽度基本相同。 蚀刻的栅极电极层形成半导体晶片上的超窄栅电极，其中硬掩模层被去除。

公开(公告)号：US06828205B2

公开(公告)日：2004-12-07

申请号：US10072798

申请日：2002-02-07

申请人： Ming-Huan Tsai ,  Ming-Jie Huang ,  Huan-Just Lin ,  Hun-Jan Tao

发明人： Ming-Huan Tsai ,  Ming-Jie Huang ,  Huan-Just Lin ,  Hun-Jan Tao

IPC分类号： H01L218222

CPC分类号： H01L21/31111 ,  H01L21/28123 ,  H01L21/32139

摘要： A method for using an isotropic wet etching process chemical process for trimming semiconductor feature sizes with improved critical dimension control including providing a hard mask overlying a substrate included in a semiconductor wafer said hard mask patterned for masking a portion of the substrate for forming a semiconductor feature according to an anisotropic plasma etching process; isotropically wet etching the hard mask to reduce a dimension of the hard mask prior to carrying out the anisotropic plasma etching process; and, anisotropically plasma etching a portion of the substrate not covered by the hard mask to form the semiconductor feature.

摘要翻译： 一种使用各向同性湿蚀刻工艺化学工艺的方法，用于修整具有改进的临界尺寸控制的半导体特征尺寸，包括提供覆盖在半导体晶片中的衬底的硬掩模，所述硬掩模被图案化以掩蔽用于形成半导体特征的衬底的一部分 根据各向异性等离子体蚀刻工艺; 在进行各向异性等离子体蚀刻工艺之前，均匀地湿式蚀刻硬掩模以减小硬掩模的尺寸; 并且各向异性等离子体蚀刻未被硬掩模覆盖的衬底的一部分以形成半导体特征。

公开(公告)号：US07023042B2

公开(公告)日：2006-04-04

申请号：US10755498

申请日：2004-01-12

申请人： Bor-Wen Chan ,  Huan-Just Lin ,  Hun-Jan Tao

发明人： Bor-Wen Chan ,  Huan-Just Lin ,  Hun-Jan Tao

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L28/88 ,  H01L27/10814 ,  H01L27/10852

摘要： A process for forming a DRAM stacked capacitor structure with increased surface area, has been developed. The process features forming lateral grooves in the sides of a polysilicon storage node structure, during a dry etching procedure used to define the storage node structure. The grooves are selectively, and laterally formed in ion implanted veins, which in turn had been placed at various depths in an intrinsic polysilicon layer via a series of ion implantation steps, each performed at a specific implant energy. An isotopic component of the storage node structure, defining dry etch procedure, selectively etches the highly doped, ion implanted veins at a greater rate than the non-ion implanted regions of polysificon, located between the ion implanted veins, resulting in a necked profile, storage node structure, featuring increased surface area as a result of the formation of the lateral grooves.

摘要翻译： 已经开发了用于形成具有增加的表面积的DRAM叠层电容器结构的工艺。 该工艺在用于限定存储节点结构的干蚀刻过程中，在多晶硅存储节点结构的侧面形成横向凹槽。 这些凹槽是选择性地和侧向地形成在离子植入的静脉中，这些静脉又通过一系列离子注入步骤而被放置在本征多晶硅层中的各种深度处，每个离子注入步骤以特定的注入能量进行。 存储节点结构的同位素组分定义了干蚀刻过程，选择性地以高于离子植入的静脉之间的聚合物的非离子注入区域的速率以更高的速率蚀刻高度掺杂的离子植入的静脉，产生颈缩轮廓， 存储节点结构，由于形成横向槽而具有增加的表面积。

公开(公告)号：US06235440B1

公开(公告)日：2001-05-22

申请号：US09434563

申请日：1999-11-12

申请人： Hun-Jan Tao ,  Huan-Just Lin ,  Fang-Cheng Chen

发明人： Hun-Jan Tao ,  Huan-Just Lin ,  Fang-Cheng Chen

IPC分类号： G03F900

CPC分类号： G03F7/70625 ,  G03F7/40 ,  H01L22/20 ,  Y10S438/949

摘要： The invention is a process for reducing variations in CD from wafer to wafer. It begins by increasing all line widths in the original pattern data file by a fixed amount that is sufficient to ensure that all lines will be wider than the lowest acceptable CD value. Using a reticle generated from this modified data file, the pattern is formed in photoresist and the resulting CD value is determined. If this turns out be outside (above) the acceptable CD range, the amount of deviation from the ideal CD value is determined and fed into suitable software that calculates the control parameters (usually time) for an ashing routine. After ashing, the lines will have been reduced in width by the amount necessary to obtain the correct CD. A fringe benefit of this trimming process is that edge roughness of the photoresist lines is reduced and line feet are removed.

摘要翻译： 本发明是减少CD从晶片到晶片的变化的方法。 它首先将原始图案数据文件中的所有行宽增加一个固定的量，这足以确保所有行都比最低可接受的CD值宽。 使用由该修改的数据文件生成的掩模版，在光致抗蚀剂中形成图案，并确定所得到的CD值。 如果事实证明在可接受的CD范围之外（以上），则确定与理想CD值的偏差量，并将其馈送到计算灰化程序的控制参数（通常为时间）的合适软件中。 灰化后，线条的宽度减小了获得正确CD所需的量。 这种修整过程的附带优点是减少了光致抗蚀剂线的边缘粗糙度并且去除了线脚。

公开(公告)号：US07947591B2

公开(公告)日：2011-05-24

申请号：US12099827

申请日：2008-04-09

申请人： Peng-Fu Hsu ,  Fong-Yu Yen ,  Yi-Shien Mor ,  Huan-Just Lin ,  Ying Jin ,  Hun-Jan Tao

发明人： Peng-Fu Hsu ,  Fong-Yu Yen ,  Yi-Shien Mor ,  Huan-Just Lin ,  Ying Jin ,  Hun-Jan Tao

IPC分类号： H01L21/3205

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L27/0922 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7833

摘要： Semiconductor devices with dual-metal gate structures and fabrication methods thereof. A semiconductor substrate with a first doped region and a second doped region separated by an insulation layer is provided. A first metal gate stack is formed on the first doped region, and a second metal gate stack is formed on the second doped region. A sealing layer is disposed on sidewalls of the first gate stack and the second gate stack. The first metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a first metal layer on the high-k dielectric layer, a metal insertion layer on the first metal layer, a second metal layer on the metal insertion layer, and a polysilicon layer on the second metal layer. The second metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a second metal layer on the high-k dielectric layer, and a polysilicon layer on the second metal layer.

摘要翻译： 具有双金属栅极结构的半导体器件及其制造方法。 提供了具有由绝缘层分隔开的第一掺杂区域和第二掺杂区域的半导体衬底。 在第一掺杂区上形成第一金属栅叠层，在第二掺杂区上形成第二金属栅叠层。 密封层设置在第一栅极堆叠和第二栅极叠层的侧壁上。 第一金属栅叠层包括界面层，界面层上的高k电介质层，高k电介质层上的第一金属层，第一金属层上的金属插入层，金属上的第二金属层 插入层和第二金属层上的多晶硅层。 第二金属栅堆叠包括界面层，界面层上的高k电介质层，高k电介质层上的第二金属层和第二金属层上的多晶硅层。

公开(公告)号：US20080188044A1

公开(公告)日：2008-08-07

申请号：US12099827

申请日：2008-04-09

申请人： Peng-Fu Hsu ,  Fong-Yu Yen ,  Yi-Shien Mor ,  Huan-Just Lin ,  Ying Jin ,  Hun-Jan Tao

发明人： Peng-Fu Hsu ,  Fong-Yu Yen ,  Yi-Shien Mor ,  Huan-Just Lin ,  Ying Jin ,  Hun-Jan Tao

IPC分类号： H01L21/8238

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L27/0922 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7833

摘要： Semiconductor devices with dual-metal gate structures and fabrication methods thereof. A semiconductor substrate with a first doped region and a second doped region separated by an insulation layer is provided. A first metal gate stack is formed on the first doped region, and a second metal gate stack is formed on the second doped region. A sealing layer is disposed on sidewalls of the first gate stack and the second gate stack. The first metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a first metal layer on the high-k dielectric layer, a metal insertion layer on the first metal layer, a second metal layer on the metal insertion layer, and a polysilicon layer on the second metal layer. The second metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a second metal layer on the high-k dielectric layer, and a polysilicon layer on the second metal layer.

公开(公告)号：US20080099851A1

公开(公告)日：2008-05-01

申请号：US11552704

申请日：2006-10-25

申请人： Peng-Fu Hsu ,  Fong-Yu Yen ,  Yi-Shien Mor ,  Huan-Just Lin ,  Ying Jin ,  Hun-Jan Tao

发明人： Peng-Fu Hsu ,  Fong-Yu Yen ,  Yi-Shien Mor ,  Huan-Just Lin ,  Ying Jin ,  Hun-Jan Tao

IPC分类号： H01L29/94 ,  H01L21/8238

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L27/0922 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7833

摘要： Semiconductor devices with dual-metal gate structures and fabrication methods thereof. A semiconductor substrate with a first doped region and a second doped region separated by an insulation layer is provided. A first metal gate stack is formed on the first doped region, and a second metal gate stack is formed on the second doped region. A sealing layer is disposed on sidewalls of the first gate stack and the second gate stack. The first metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a first metal layer on the high-k dielectric layer, a metal insertion layer on the first metal layer, a second metal layer on the metal insertion layer, and a polysilicon layer on the second metal layer. The second metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a second metal layer on the high-k dielectric layer, and a polysilicon layer on the second metal layer.

摘要翻译： 具有双金属栅极结构的半导体器件及其制造方法。 提供了具有由绝缘层分隔开的第一掺杂区域和第二掺杂区域的半导体衬底。 在第一掺杂区上形成第一金属栅叠层，在第二掺杂区上形成第二金属栅叠层。 密封层设置在第一栅极堆叠和第二栅极叠层的侧壁上。 第一金属栅叠层包括界面层，界面层上的高k电介质层，高k电介质层上的第一金属层，第一金属层上的金属插入层，金属上的第二金属层 插入层和第二金属层上的多晶硅层。 第二金属栅堆叠包括界面层，界面层上的高k电介质层，高k电介质层上的第二金属层和第二金属层上的多晶硅层。

公开(公告)号：US06706591B1

公开(公告)日：2004-03-16

申请号：US10054561

申请日：2002-01-22

申请人： Bor-Wen Chan ,  Huan-Just Lin ,  Hun-Jan Tao

发明人： Bor-Wen Chan ,  Huan-Just Lin ,  Hun-Jan Tao

IPC分类号： H01L218242

CPC分类号： H01L28/88 ,  H01L27/10814 ,  H01L27/10852

摘要： A process for forming a DRAM stacked capacitor structure with increased surface area, has been developed. The process features forming lateral grooves in the sides of a polysilicon storage node structure, during a dry etching procedure used to define the storage node structure. The grooves are selectively, and laterally formed in ion implanted veins, which in turn had been placed at various depths in an intrinsic polysilicon layer via a series of ion implantation steps, each performed at a specific implant energy. An isotopic component of the storage node structure, defining dry etch procedure, selectively etches the highly doped, ion implanted veins at a greater rate than the non-ion implanted regions of polysilicon, located between the ion implanted veins, resulting in a necked profile, storage node structure, featuring increase surface area as a result of the formation of the lateral grooves.

摘要翻译： 已经开发了用于形成具有增加的表面积的DRAM叠层电容器结构的工艺。 该工艺在用于限定存储节点结构的干蚀刻过程中，在多晶硅存储节点结构的侧面形成横向凹槽。 这些凹槽是选择性地和侧向地形成在离子植入的静脉中，这些静脉又通过一系列离子注入步骤而被放置在本征多晶硅层中的各种深度处，每个离子注入步骤以特定的注入能量进行。 定义干法刻蚀程序的存储节点结构的同位素组分以比位于离子植入静脉之间的多晶硅的非离子注入区域更大的速率选择性地蚀刻高掺杂离子植入的静脉，导致颈缩轮廓， 存储节点结构，由于形成横向槽而具有增加的表面积。