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    Conformal liner for gap-filling
    1.
    发明申请
    Conformal liner for gap-filling 审中-公开
    用于间隙填充的保形衬套

    公开(公告)号：US20080096364A1

    公开(公告)日：2008-04-24

    申请号：US11582442

    申请日：2006-10-18

    申请人： Erik Wilson ,  Minh-Van Ngo ,  Hieu Pham ,  Robert Huertas ,  Lu You ,  Hirokazu Tokuno ,  Alexander Nickel ,  Minh Tran

    发明人： Erik Wilson ,  Minh-Van Ngo ,  Hieu Pham ,  Robert Huertas ,  Lu You ,  Hirokazu Tokuno ,  Alexander Nickel ,  Minh Tran

    IPC分类号： H01L21/76

    CPC分类号： H01L21/823468 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/823437

    摘要： Gap filling between features which are closely spaced is significantly improved by initially depositing a thin conformal layer followed by depositing a layer of gap filling dielectric material. Embodiments include depositing a thin conformal layer of silicon nitride or silicon oxide, as by atomic layer deposition or pulsed layer deposition, into the gap between adjacent gate electrode structures such that it flows into undercut regions of dielectric spacers on side surfaces of the gate electrode structures, and then depositing a layer of BPSG or P-HDP oxide on the thin conformal layer into the gap. Embodiments further include depositing the layers at a temperature less than 430° C., as by depositing a P-HDP oxide after depositing the conformal liner when the gate electrode structures include a layer of nickel silicide.

    摘要翻译： 通过初始沉积薄的共形层，然后沉积一层间隙填充电介质材料，密切间隔的特征之间的间隙填充显着改善。 实施例包括通过原子层沉积或脉冲层沉积将氮化硅或氧化硅的薄保形层沉积到相邻栅电极结构之间的间隙中，使得其流到栅电极结构的侧表面上的电介质间隔物的底切区域 ，然后在薄的共形层上沉积一层BPSG或P-HDP氧化物到间隙中。 实施例还包括在低于430℃的温度下沉积层，如通过在栅极电极结构包括硅化镍层沉积保形衬垫之后沉积P-HDP氧化物。

    Gap-filling with uniform properties
    3.
    发明授权
    Gap-filling with uniform properties 有权
    间隙填充均匀性

    公开(公告)号：US08415256B1

    公开(公告)日：2013-04-09

    申请号：US12982364

    申请日：2010-12-30

    申请人： Alexander Nickel ,  Lu You ,  Hirokazu Tokuno ,  Minh Tran ,  Minh Van Ngo ,  Hieu Pham ,  Erik Wilson ,  Robert Huertas

    发明人： Alexander Nickel ,  Lu You ,  Hirokazu Tokuno ,  Minh Tran ,  Minh Van Ngo ,  Hieu Pham ,  Erik Wilson ,  Robert Huertas

    IPC分类号： H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/022 ,  H01L21/02348 ,  H01L21/76224 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76837

    摘要： During semiconductor fabrication homogeneous gap-filling is achieved by depositing a thin dielectric layer into the gap, post deposition curing, and then repeating deposition and post deposition curing until gap-filling is completed. Embodiments include depositing a layer of low deposition temperature gap-fill dielectric into a high aspect ratio opening, such as a shallow trench or a gap between closely spaced apart gate electrode structures, as at a thickness of about 10 Å to about 500 Å, curing after deposition, as by UV radiation or by heating at a temperature of about 400° C. to about 1000° C., depositing another layer of low deposition temperature gap-filled dielectric, and curing after deposition. Embodiments include separately depositing and separately curing multiple layers.

    摘要翻译： 在半导体制造期间，通过将薄介电层沉积到间隙中，后沉积固化，然后重复沉积和后沉积固化直到间隙填充完成来实现均匀间隙填充。 实施例包括将低沉积温度间隙填充电介质的层沉积到高纵横比开口中，例如浅沟槽或紧密间隔开的栅电极结构之间的间隙，其厚度约为至约500，固化 在沉积之后，如通过UV辐射或在约400℃至约1000℃的温度下加热，沉积另一层低沉积温度充满间隙的电介质，并在沉积后固化。 实施例包括分别沉积和分别固化多层。

    Gap-filling with uniform properties
    4.
    发明授权
    Gap-filling with uniform properties 有权
    间隙填充均匀性

    公开(公告)号：US07884030B1

    公开(公告)日：2011-02-08

    申请号：US11408086

    申请日：2006-04-21

    申请人： Alexander Nickel ,  Lu You ,  Hirokazu Tokuno ,  Minh Tran ,  Minh Van Ngo ,  Hieu Pham ,  Erik Wilson ,  Robert Huertas

    发明人： Alexander Nickel ,  Lu You ,  Hirokazu Tokuno ,  Minh Tran ,  Minh Van Ngo ,  Hieu Pham ,  Erik Wilson ,  Robert Huertas

    IPC分类号： H01L21/31 ,  H01L21/469 ,  H01L23/58

    CPC分类号： H01L21/022 ,  H01L21/02348 ,  H01L21/76224 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76837

    摘要： During semiconductor fabrication homogeneous gap-filling is achieved by depositing a thin dielectric layer into the gap, post deposition curing, and then repeating deposition and post deposition curing until gap-filling is completed. Embodiments include depositing a layer of low deposition temperature gap-fill dielectric into a high aspect ratio opening, such as a shallow trench or a gap between closely spaced apart gate electrode structures, as at a thickness of about 10 Å to about 500 Å, curing after deposition, as by UV radiation or by heating at a temperature of about 400° C. to about 1000° C., depositing another layer of low deposition temperature gap-filled dielectric, and curing after deposition. Embodiments include separately depositing and separately curing multiple layers.

    摘要翻译： 在半导体制造期间，通过将薄介电层沉积到间隙中，后沉积固化，然后重复沉积和后沉积固化直到间隙填充完成来实现均匀间隙填充。 实施例包括将低沉积温度间隙填充电介质的层沉积到高纵横比开口中，例如浅沟槽或紧密间隔开的栅电极结构之间的间隙，其厚度约为至约500，固化 在沉积之后，如通过UV辐射或在约400℃至约1000℃的温度下加热，沉积另一层低沉积温度充满间隙的电介质，并在沉积后固化。 实施例包括分别沉积和分别固化多层。

    Active-passive photonic integrated circuit platform
    7.
    发明授权
    Active-passive photonic integrated circuit platform 有权

    公开(公告)号：US11480734B2

    公开(公告)日：2022-10-25

    申请号：US16600349

    申请日：2019-10-11

    申请人： Hyundai Park ,  Tin Komljenovic ,  Chong Zhang ,  Minh Tran

    发明人： Hyundai Park ,  Tin Komljenovic ,  Chong Zhang ,  Minh Tran

    IPC分类号： G02B6/12 ,  G02B6/26 ,  G02B6/42 ,  G02B6/14 ,  G02B6/122 ,  G02B6/13

    摘要： A device providing efficient transformation between an initial optical mode and a second optical mode includes first, second and third elements fabricated on a common substrate. The first element includes first and second active sub-layers supporting initial and final optical modes with efficient mode transformation therebetween. The second element includes a passive waveguide structure supporting a second optical mode. The third element, at least partly butt-coupled to the first element, includes an intermediate waveguide structure supporting an intermediate optical mode. If the final optical mode differs from the second optical mode by more than a predetermined amount, a tapered waveguide structure in the second or third elements facilitates efficient transformation between the intermediate optical mode and the second optical mode. Precise alignment of sub-elements formed in one of the elements, relative to sub-elements formed in another one of the elements, is defined using lithographic alignment marks.

    INTEGRATED ACTIVE DEVICES WITH ENHANCED OPTICAL COUPLING TO DIELECTRIC WAVEGUIDES
    8.
    发明申请
    INTEGRATED ACTIVE DEVICES WITH ENHANCED OPTICAL COUPLING TO DIELECTRIC WAVEGUIDES 有权

    公开(公告)号：US20210373235A1

    公开(公告)日：2021-12-02

    申请号：US17015785

    申请日：2020-09-09

    申请人： Chong Zhang ,  Hyun Dai Park ,  Minh Tran ,  Tin Komljenovic

    发明人： Chong Zhang ,  Hyun Dai Park ,  Minh Tran ,  Tin Komljenovic

    IPC分类号： G02B6/122 ,  G02B6/12 ,  H01S5/10 ,  H01S5/026

    摘要： A device comprises first, second and third elements fabricated on a common substrate. The first element comprises an active waveguide structure comprising: one portion, of effective cross-sectional area A1, supporting a first optical mode; and a second portion, butt-coupled to the first portion, of effective cross-sectional area A2>A1. The second element comprises a passive waveguide structure supporting a second optical mode. The third element, at least partly butt-coupled to the second portion, comprises an intermediate waveguide structure supporting intermediate optical modes. If the first optical mode differs from the second optical mode by more than a predetermined amount, a tapered waveguide structure in at least one of the second and third elements facilitates efficient adiabatic transformation between the first optical mode and one intermediate optical mode. No adiabatic transformation occurs between any intermediate optical mode and the first optical mode. Mutual alignments of the elements are defined using lithographic marks.