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    METHODS FOR FORMING A MEMORY CELL HAVING A TOP OXIDE SPACER
    1.
    发明申请
    METHODS FOR FORMING A MEMORY CELL HAVING A TOP OXIDE SPACER 有权
    用于形成具有顶部氧化物间隔物的存储单元的方法

    公开(公告)号：US20120181601A1

    公开(公告)日：2012-07-19

    申请号：US13428848

    申请日：2012-03-23

    申请人： Shenqing FANG ,  Angela HUI ,  Gang XUE ,  Alexander NICKEL ,  Kashmir SAHOTA ,  Scott BELL ,  Chun CHEN ,  Wai LO

    发明人： Shenqing FANG ,  Angela HUI ,  Gang XUE ,  Alexander NICKEL ,  Kashmir SAHOTA ,  Scott BELL ,  Chun CHEN ,  Wai LO

    IPC分类号： H01L29/792

    CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L29/792

    摘要： Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.

    摘要翻译： 公开了制造具有间隔层的半导体存储单元的方法。 一种方法包括在衬底中形成多个源极/漏极区域，其中多个源极/漏极区域形成在沟槽之间，在多个源极/漏极区域上方和沟槽中形成第一氧化物层，形成电荷存储层 在电荷存储层的分离部分之间，在形成空间的沟槽中分离电荷存储层。 该方法还包括形成间隔层以填充电荷存储层的分离部分之间的空间并在空间上方上升预定距离。 在电荷存储层和间隔层上方形成第二氧化物层，并且在第二氧化物层上方形成多晶硅层。

    Fastening device for a line
    2.
    发明授权
    Fastening device for a line 有权
    紧固装置为一条线

    公开(公告)号：US08017870B2

    公开(公告)日：2011-09-13

    申请号：US12302087

    申请日：2007-07-13

    申请人： Keiji Kawakami ,  Alexander Nickel

    发明人： Keiji Kawakami ,  Alexander Nickel

    IPC分类号： H02G3/00

    CPC分类号： B60R16/0222 ,  H02G3/0475 ,  Y10T16/063

    摘要： A fastening device for a line, in particular for an electric cable (12) in a motor vehicle, is proposed, the fastening device having a bush (10) which can be locked in a holder (18), at least partially surrounds the line, is made of elastically deformable material and is fastened releaseably in a cutout (16) of the holder (18) by means of a contour (14). According to the invention, the surface of a bush (10), which is injection-moulded from plastic, is of segmented design in order to obtain easier deformability of the bush when fitting it into an associated holder (18).

    摘要翻译： 提出了一种用于线路的紧固装置，特别是用于机动车辆中的电缆（12）的紧固装置，所述紧固装置具有可锁定在保持器（18）中的衬套（10），至少部分地围绕线 由弹性变形材料制成，并且通过轮廓（14）可释放地固定在保持器（18）的切口（16）中。 根据本发明，由塑料注射成型的衬套（10）的表面是分段设计的，以便在将衬套安装到相关联的保持器（18）中时更容易地变形。

    FLASH MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME
    3.
    发明申请
    FLASH MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME 审中-公开
    闪存存储器件及其制造方法

    公开(公告)号：US20080153236A1

    公开(公告)日：2008-06-26

    申请号：US11615425

    申请日：2006-12-22

    申请人： Ning Cheng ,  Kuo-Tung Chang ,  Hiroyuki Kinoshita ,  Minh-Van Ngo ,  Fred Cheung ,  Alexander Nickel

    发明人： Ning Cheng ,  Kuo-Tung Chang ,  Hiroyuki Kinoshita ,  Minh-Van Ngo ,  Fred Cheung ,  Alexander Nickel

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66833 ,  H01L27/115 ,  H01L27/11568

    摘要： Flash memory devices and methods for fabricating the same are provided. A method for fabricating a memory device comprises the steps of fabricating a first gate stack and a second gate stack overlying a P-type silicon substrate and implanting an impurity dopant into the substrate substantially between the first gate stack and the second gate stack to form an impurity-doped region of the substrate. A channel region underlies the first gate stack adjacent to the impurity-doped region. An intrinsically tensile-stressed insulating member is formed between the first and the second gate stacks and overlying the impurity-doped region. The tensile-stressed insulating member causes a uniaxial lateral tensile stress to be transmitted to the first channel region. A word line is formed overlying the intrinsically tensile-stressed insulating member and in electrical contact with the first gate stack and the second gate stack.

    摘要翻译： 提供闪存器件及其制造方法。 一种用于制造存储器件的方法包括以下步骤：制造覆盖P型硅衬底的第一栅极堆叠和第二栅极堆叠，并且基本上在第一栅极堆叠和第二栅极堆叠之间将杂质掺杂剂注入到衬底中，以形成 衬底的杂质掺杂区域。 位于与杂质掺杂区相邻的第一栅叠层下方的沟道区。 在第一和第二栅极堆叠之间并且覆盖杂质掺杂区域上形成本征拉伸应力的绝缘构件。 拉伸应力绝缘构件使单向横向拉伸应力传递到第一沟道区域。 在本征拉伸应力绝缘构件上形成字线并且与第一栅极堆叠和第二栅极堆叠电接触。

    Methods for forming a memory cell having a top oxide spacer
    4.
    发明授权
    Methods for forming a memory cell having a top oxide spacer 有权
    形成具有顶部氧化物间隔物的存储单元的方法

    公开(公告)号：US08384146B2

    公开(公告)日：2013-02-26

    申请号：US13428848

    申请日：2012-03-23

    申请人： Shenqing Fang ,  Angela Hui ,  Gang Xue ,  Alexander Nickel ,  Kashmir Sahota ,  Scott Bell ,  Chun Chen ,  Wai Lo

    发明人： Shenqing Fang ,  Angela Hui ,  Gang Xue ,  Alexander Nickel ,  Kashmir Sahota ,  Scott Bell ,  Chun Chen ,  Wai Lo

    IPC分类号： H01L29/76

    CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L29/792

    摘要： Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.

    摘要翻译： 公开了制造具有间隔层的半导体存储单元的方法。 一种方法包括在衬底中形成多个源极/漏极区域，其中多个源极/漏极区域形成在沟槽之间，在多个源极/漏极区域上方和沟槽中形成第一氧化物层，形成电荷存储层 在电荷存储层的分离部分之间，在形成空间的沟槽中分离电荷存储层。 该方法还包括形成间隔层以填充电荷存储层的分离部分之间的空间并在空间上方上升预定距离。 在电荷存储层和间隔层上方形成第二氧化物层，并且在第二氧化物层上方形成多晶硅层。

    Conformal liner for gap-filling
    7.
    发明申请
    Conformal liner for gap-filling 审中-公开
    用于间隙填充的保形衬套

    公开(公告)号：US20080096364A1

    公开(公告)日：2008-04-24

    申请号：US11582442

    申请日：2006-10-18

    申请人： Erik Wilson ,  Minh-Van Ngo ,  Hieu Pham ,  Robert Huertas ,  Lu You ,  Hirokazu Tokuno ,  Alexander Nickel ,  Minh Tran

    发明人： Erik Wilson ,  Minh-Van Ngo ,  Hieu Pham ,  Robert Huertas ,  Lu You ,  Hirokazu Tokuno ,  Alexander Nickel ,  Minh Tran

    IPC分类号： H01L21/76

    CPC分类号： H01L21/823468 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/823437

    摘要： Gap filling between features which are closely spaced is significantly improved by initially depositing a thin conformal layer followed by depositing a layer of gap filling dielectric material. Embodiments include depositing a thin conformal layer of silicon nitride or silicon oxide, as by atomic layer deposition or pulsed layer deposition, into the gap between adjacent gate electrode structures such that it flows into undercut regions of dielectric spacers on side surfaces of the gate electrode structures, and then depositing a layer of BPSG or P-HDP oxide on the thin conformal layer into the gap. Embodiments further include depositing the layers at a temperature less than 430° C., as by depositing a P-HDP oxide after depositing the conformal liner when the gate electrode structures include a layer of nickel silicide.

    摘要翻译： 通过初始沉积薄的共形层，然后沉积一层间隙填充电介质材料，密切间隔的特征之间的间隙填充显着改善。 实施例包括通过原子层沉积或脉冲层沉积将氮化硅或氧化硅的薄保形层沉积到相邻栅电极结构之间的间隙中，使得其流到栅电极结构的侧表面上的电介质间隔物的底切区域 ，然后在薄的共形层上沉积一层BPSG或P-HDP氧化物到间隙中。 实施例还包括在低于430℃的温度下沉积层，如通过在栅极电极结构包括硅化镍层沉积保形衬垫之后沉积P-HDP氧化物。

    Gap-filling with uniform properties
    8.
    发明授权
    Gap-filling with uniform properties 有权
    间隙填充均匀性

    公开(公告)号：US08415256B1

    公开(公告)日：2013-04-09

    申请号：US12982364

    申请日：2010-12-30

    申请人： Alexander Nickel ,  Lu You ,  Hirokazu Tokuno ,  Minh Tran ,  Minh Van Ngo ,  Hieu Pham ,  Erik Wilson ,  Robert Huertas

    发明人： Alexander Nickel ,  Lu You ,  Hirokazu Tokuno ,  Minh Tran ,  Minh Van Ngo ,  Hieu Pham ,  Erik Wilson ,  Robert Huertas

    IPC分类号： H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/022 ,  H01L21/02348 ,  H01L21/76224 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76837

    摘要： During semiconductor fabrication homogeneous gap-filling is achieved by depositing a thin dielectric layer into the gap, post deposition curing, and then repeating deposition and post deposition curing until gap-filling is completed. Embodiments include depositing a layer of low deposition temperature gap-fill dielectric into a high aspect ratio opening, such as a shallow trench or a gap between closely spaced apart gate electrode structures, as at a thickness of about 10 Å to about 500 Å, curing after deposition, as by UV radiation or by heating at a temperature of about 400° C. to about 1000° C., depositing another layer of low deposition temperature gap-filled dielectric, and curing after deposition. Embodiments include separately depositing and separately curing multiple layers.

    摘要翻译： 在半导体制造期间，通过将薄介电层沉积到间隙中，后沉积固化，然后重复沉积和后沉积固化直到间隙填充完成来实现均匀间隙填充。 实施例包括将低沉积温度间隙填充电介质的层沉积到高纵横比开口中，例如浅沟槽或紧密间隔开的栅电极结构之间的间隙，其厚度约为至约500，固化 在沉积之后，如通过UV辐射或在约400℃至约1000℃的温度下加热，沉积另一层低沉积温度充满间隙的电介质，并在沉积后固化。 实施例包括分别沉积和分别固化多层。