公开(公告)号：US4268875A

公开(公告)日：1981-05-19

申请号：US031515

申请日：1979-04-19

申请人： Minoru Morio ,  Masahiro Kambara ,  Yukio Kubota ,  Keitaro Yamashita

发明人： Minoru Morio ,  Masahiro Kambara ,  Yukio Kubota ,  Keitaro Yamashita

IPC分类号： H04N5/93 ,  G11B5/027 ,  G11B5/588 ,  H04N9/893 ,  H04N5/78

CPC分类号： H04N9/893 ,  G11B5/588

摘要： In a recording and reproducing apparatus in which a video signal is recorded by at least one rotary head in successive parallel tracks on a recording medium while the latter is being driven at a predetermined or standard speed in a direction to which said tracks are skewed, and in which the recorded video signal is reproduced by the rotary head repeatedly scanning the recording medium while the latter is selectively driven at the standard speed, as in the normal reproducing mode, or at an arbitrary speed other than such standard speed, for example, at zero speed for the still-motion reproducing mode, or at speeds less than and greater than the standard speed for the slow-motion and quick-motion reproducing modes, respectively; a variable delay circuit is operative during reproducing with the recording medium being driven at an arbitrary speed other than standard speed for variably delaying the video signal reproduced by said rotary head, and a control circuit controls the amounts by which the variable delay circuit delays the reproduced video signal in accordance with the arbitrary speed to cause fields of the reproduced video signal which are contiguous or next adjacent in point of time to be continuous in the delayed video signal and to contain respective horizontal synchronizing signals which are in predetermined phase relationships to each other, that is, precisely in phase or out of phase by one-half horizontal period, as when even- and odd-numbered fields are to be interlaced.

摘要翻译： 在记录和再现装置中，其中视频信号由记录介质上的连续平行轨道中的至少一个旋转磁头记录，而后者以预定或标准速度在所述轨道倾斜的方向上被驱动，以及 其中记录的视频信号由旋转头重复地扫描记录介质，而后者以标准速度选择性地被驱动，如在正常再现模式中，或以除这种标准速度以外的任意速度，例如在 用于静止运动再现模式的零速度或小于和大于慢动作和快速运动再现模式的标准速度的速度; 可变延迟电路在再现期间操作，其中以不同于标准速度的任意速度驱动记录介质，用于可变地延迟由所述旋转磁头再现的视频信号，并且控制电路控制可变延迟电路延迟再现的数量 视频信号根据任意速度使得在延迟视频信号中连续或相邻连续或相邻的重放视频信号的场相互连续，并且包含彼此处于预定相位关系的各个水平同步信号 ，也就是说，当偶数和奇数场将被隔行扫描时，精确地相位或相位相差半个水平周期。

公开(公告)号：US08860652B2

公开(公告)日：2014-10-14

申请号：US13593424

申请日：2012-08-23

申请人： Keitaro Yamashita

发明人： Keitaro Yamashita

IPC分类号： G09G3/36

CPC分类号： G09G3/3674 ,  G09G2310/0286 ,  G09G2320/0223

摘要： A shift register is provided. In each of successively cascaded shift register units, for a first switch, control and output terminals are coupled to a first node and an output node respectively, and an input terminal receives a first clock signal. For a second switch, input and output terminals are coupled to the control terminal of the second switch and the first node respectively. For a third switch, a control terminal is coupled to the first node, and an input terminal receives the first clock signal. A first capacitor is coupled between an output terminal of the third switch and the first node. For a fourth switch, an input terminal is coupled to the first node, and an output terminal is coupled to a low voltage terminal. For a current shift register, a control terminal of the second switch receives an output signal generated by previous shift register unit.

摘要翻译： 提供移位寄存器。 在连续级联移位寄存器单元的每一个中，对于第一开关，控制和输出端分别耦合到第一节点和输出节点，并且输入端子接收第一时钟信号。 对于第二开关，输入和输出端分别耦合到第二开关的控制端和第一节点。 对于第三开关，控制端子耦合到第一节点，并且输入端子接收第一时钟信号。 第一电容器耦合在第三开关的输出端和第一节点之间。 对于第四开关，输入端子耦合到第一节点，并且输出端子耦合到低电压端子。 对于当前移位寄存器，第二开关的控制端子接收由先前移位寄存器单元产生的输出信号。

公开(公告)号：US08736591B2

公开(公告)日：2014-05-27

申请号：US13278538

申请日：2011-10-21

申请人： Keitaro Yamashita

发明人： Keitaro Yamashita

IPC分类号： G09G3/36 ,  G06F3/038 ,  G09G5/00

CPC分类号： G09G3/3648 ,  G09G2300/0439 ,  G09G2300/0842 ,  G09G2310/0251 ,  G09G2310/08 ,  G09G2320/0247

摘要： A display device where a memory circuit is installed into each pixel without generating flicker, including a plurality of pixels arranged in a matrix, wherein each pixel has a light-transmissive element controlling the amount of transmissive light in response to a voltage difference between a first electrode and a second electrode, a memory circuit storing the voltage level of the first electrode, and a controller. In the case where the first electrode has a positive voltage level with respect to the second electrode at a refreshing timing, the controller makes the memory circuit store the voltage level of the first electrode, applies a first predetermined voltage to the second electrode to increase the voltage level of the first electrode by the first predetermined voltage, and discharges the first electrode so that the first electrode has a negative voltage level with respect to the second electrode.

摘要翻译： 一种显示装置，其中存储电路被安装到每个像素中而不产生闪烁，包括排列成矩阵的多个像素，其中每个像素具有光传输元件，其响应于第一 电极和第二电极，存储第一电极的电压电平的存储电路和控制器。 在第一电极在刷新定时相对于第二电极具有正电压电平的情况下，控制器使存储电路存储第一电极的电压电平，向第二电极施加第一预定电压以增加第 第一电极的电压电平达到第一预定电压，并且使第一电极放电，使得第一电极相对于第二电极具有负电压电平。

公开(公告)号：US08665248B2

公开(公告)日：2014-03-04

申请号：US12332751

申请日：2008-12-11

申请人： Keitaro Yamashita

发明人： Keitaro Yamashita

IPC分类号： G06F3/038

CPC分类号： G09G3/3677

摘要： A drive circuit is disclosed. The drive circuit includes a first p-typed thin film transistor (PTFT), a second PTFT, a first n-typed thin film transistor (NTFT), a second NTFT and a capacitor. The drain of the first PTFT is coupled to a first electrical line, and the gate thereof is coupled to a first clock line. The drain of the second PTFT is coupled to a second clock line, and the source thereof is coupled to an output. The source of the first NTFT is coupled to a second electrical line, and the gate thereof is couple to an output of a preceding drive circuit. The source of the second NTFT is couple to a third electrical line, the gate thereof is coupled to a third clock line, and the drain thereof is coupled to the output. The capacitor has one end coupled to the second electrical line, while the other end is coupled to the source of the first PTFT, the drain of the first NTFT and the gate of the second PTFT.

摘要翻译： 公开了一种驱动电路。 驱动电路包括第一p型薄膜晶体管（PTFT），第二PTFT，第一n型薄膜晶体管（NTFT），第二NTFT和电容器。 第一PTFT的漏极耦合到第一电线，并且其栅极耦合到第一时钟线。 第二PTFT的漏极耦合到第二时钟线，并且其源极耦合到输出端。 第一NTFT的源极耦合到第二电线，并且其栅极耦合到先前的驱动电路的输出端。 第二NTFT的源耦合到第三电线，其栅极耦合到第三时钟线，并且其漏极耦合到输出端。 电容器具有耦合到第二电线的一端，而另一端耦合到第一PTFT的源极，第一NTFT的漏极和第二PTFT的栅极。

公开(公告)号：US07948295B2

公开(公告)日：2011-05-24

申请号：US12404112

申请日：2009-03-13

申请人： Keitaro Yamashita

发明人： Keitaro Yamashita

IPC分类号： H03K17/00

CPC分类号： H03K17/693 ,  G09G3/3648 ,  G09G3/3688 ,  G09G2300/0828 ,  G09G2300/0842 ,  G09G2310/0297 ,  H03K17/007

摘要： A demultiplexer includes an input terminal for providing an input signal, a plurality of output terminals for outputting the input signal, and a switching circuit coupled among the input terminal and the plurality of output terminals, and outputting the input signal selectively from the plurality of output terminals according to a plurality of control signals provided to a plurality of control terminals. For miniaturizing the demultiplexer, the switching circuit includes one or more switch elements connected between the input terminal and each of the output terminals in series, wherein at least two of the switch elements coupled to different output terminals are simultaneously switched in response to one control signal from the plurality of control terminals.

摘要翻译： 解复用器包括用于提供输入信号的输入端子，用于输出输入信号的多个输出端子以及耦合在输入端子和多个输出端子之间的开关电路，并且从多个输出端选择性地输出输入信号 终端根据提供给多个控制终端的多个控制信号。 为了使多路分解器小型化，开关电路包括串联连接在输入端和每个输出端之间的一个或多个开关元件，其中响应一个控制信号同时切换耦合到不同输出端的至少两个开关元件 从多个控制终端。

公开(公告)号：US20100177083A1

公开(公告)日：2010-07-15

申请号：US12652717

申请日：2010-01-05

申请人： Keitaro Yamashita

发明人： Keitaro Yamashita

IPC分类号： G06F3/038 ,  G09G3/20 ,  G09G3/36 ,  G09G3/32

CPC分类号： G09G3/20 ,  G09G3/3225 ,  G09G3/3648 ,  G09G2300/0852 ,  G09G2310/06

摘要： A display device whose pixels being embedded with a memory is disclosed. These pixels each includes: a capacitor; a switching unit between the display unit and the capacitor, being turning on during the sampling period; and a voltage detecting circuit for detecting the voltage between the capacitor and the switching unit. Besides, the display unit also includes: a first capacitor voltage source connected to a terminal of the capacitor which is not connected to the voltage detecting circuit, and applying a predetermined voltage within the variation range of the voltage state of the display unit on the capacitor in the sampling period; and/or a second capacitor voltage source, being connected to a terminal of the display unit which is not connected to the switching unit, and applying a predetermined voltage within the variation range of the voltage state of the display unit on the display unit in the sampling period.

摘要翻译： 公开了一种其嵌入存储器的像素的显示装置。 这些像素包括：电容器; 显示单元和电容器之间的切换单元在采样周期期间导通; 以及用于检测电容器和开关单元之间的电压的电压检测电路。 此外，显示单元还包括：连接到电容器的未连接到电压检测电路的端子的第一电容器电压源，并且在电容器的显示单元的电压状态的变化范围内施加预定电压 在抽样期间 和/或第二电容器电压源，连接到未连接到开关单元的显示单元的端子，并且在显示单元的显示单元的电压状态的变化范围内施加预定电压 抽样期。

公开(公告)号：US20100001970A1

公开(公告)日：2010-01-07

申请号：US12497451

申请日：2009-07-02

申请人： Keitaro Yamashita

发明人： Keitaro Yamashita

IPC分类号： G06F3/041

CPC分类号： G06F3/0412 ,  G02F1/13338 ,  G02F2201/40 ,  G06F3/045

摘要： An active matrix display apparatus with touch sensing function having high aperture ratio includes a plurality of pixels, having respective pixels arrayed as a matrix, positioned at intersections of source lines of respective columns and gate lines of respective rows, each pixel having a thin film transistor and a liquid crystal element, which is positioned between a drain of thin film transistors and a common line; and a touch switch unit having touch sensing transistors and a mechanical switch, which is positioned between two adjacent pixels in an identical column. The gates of the touch sensing transistors are coupled to the gate lines of the two adjacent pixels wherein the touch sensing transistors coupled in series and the mechanical switch shared by the adjacent pixels, are coupled between the source line of the identical column and the common line.

摘要翻译： 具有高开口率的触摸感测功能的有源矩阵显示装置包括多个像素，其具有排列成矩阵的各个像素，位于相应列的源极线和各行栅极线的交点处，每个像素具有薄膜晶体管 以及位于薄膜晶体管的漏极和公共线之间的液晶元件; 以及触摸开关单元，其具有触摸感测晶体管和位于相同列中的两个相邻像素之间的机械开关。 触摸感测晶体管的栅极耦合到两个相邻像素的栅极线，其中串联耦合的触摸感测晶体管和由相邻像素共享的机械开关耦合在相同列的源极线和公共线之间 。

公开(公告)号：US07579901B2

公开(公告)日：2009-08-25

申请号：US11578997

申请日：2005-04-25

申请人： Keitaro Yamashita

发明人： Keitaro Yamashita

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： H02M3/073 ,  H02M1/36

摘要： It is an object of the present invention to reliably avoid problems with a load connected when stopping the operation of a charge pump circuit. The charge pump circuit is provided with a first switching element (S1) connected to a power supply, a second switching element (S2) connected to a load (102)and a capacitor element (Cp) connected between the first switching element (S1) and the second switching element (S2), and moves charge in a direction opposite to the direction in which charge moves during normal operation by inverting the phase of any one of clock signals applied to the first switching element (S1), second switching element (S2) and capacitor element (Cp) during normal operation.

摘要翻译： 本发明的目的是可靠地避免在停止电荷泵电路的操作时所连接的负载的问题。 电荷泵电路设置有连接到电源的第一开关元件（S1），连接到负载（102）的第二开关元件（S2）和连接在第一开关元件（S1）之间的电容元件（Cp） 和第二开关元件（S2），通过使施加到第一开关元件（S1）的时钟信号中的任何一个的相位相反，第二开关元件（S1）和第二开关元件（S2）的相位相反地沿与正常工作期间的充电移动方向相反的方向移动电荷， S2）和电容元件（Cp）。

公开(公告)号：US20080278459A1

公开(公告)日：2008-11-13

申请号：US11664224

申请日：2005-10-13

申请人： Keitaro Yamashita

发明人： Keitaro Yamashita

IPC分类号： G06F3/042

CPC分类号： G06K9/0004

摘要： A display device which can authenticate fingerprint without a fingerprint sensor device and can be prevented from large size or reduced the size. A display device (1) is provided with a pixel or sub pixel comprising a photo diode (11) for detecting a light from a object, a holding capacitor (13) for holding a voltage (Vn1) corresponding to an intensity of the light detected by the photo diode (11), and a refreshing means (18) for writing a voltage (Vdd or Vss) into the holding capacitor (13) (node N1) on the basis of the voltage Vn1 held in the holding capacitor (13).

摘要翻译： 可以在没有指纹传感器装置的情况下认证指纹并且可以防止大尺寸或减小尺寸的显示装置。 显示装置（1）设置有像素或子像素，该像素或子像素包括用于检测来自物体的光的光电二极管（11），用于保持与光强度相对应的电压（Vn 1）的保持电容器（13） 由光电二极管（11）检测，以及刷新装置（18），用于根据保持在保持电容器（11）中的电压Vn 1将电压（Vdd或Vss）写入保持电容器（13）（节点N1） （13）。

公开(公告)号：US20070247478A1

公开(公告)日：2007-10-25

申请号：US11659866

申请日：2005-08-11

申请人： Shuji Hagino ,  Hidetoshi Watanabe ,  Akihiro Iwatsu ,  Keitaro Yamashita

发明人： Shuji Hagino ,  Hidetoshi Watanabe ,  Akihiro Iwatsu ,  Keitaro Yamashita

IPC分类号： G09G5/02

CPC分类号： G09G3/3674 ,  G09G3/3614 ,  G09G3/3648 ,  G09G2310/0213 ,  G09G2310/0224 ,  G09G2320/0209 ,  G09G2320/0233 ,  G09G2330/021

摘要： The invention aims at preventing an occurrence of artefacts while reducing power consumption. A matrix addressing method for alternately driving pixels. The frame period of the images is formed by successively sequencing on a time series a plurality of block periods, the block periods each being composed of a first half block being a period for successively sequencing on a time series application timings of the pixel voltages for one or more row electrodes to be provided with one polarity, the second half block being a period for successively sequencing on a time series application timings of the pixel voltages for one or more row electrodes to be provided with the other polarity. Ones of even-numbered row electrodes and odd-numbered row electrodes in arrangement order on the display screen are selected in the first half block. The others spatially adjoining the ones are selected in the second half block. A row electrode selecting order in the first half block and a row electrode selecting order in the second half block during one frame period are made differed from orders in the corresponding half blocks during the other frame period, respectively, so as to mitigate block-period-base visual artefact.

摘要翻译： 本发明旨在在减少功耗的同时防止伪影的发生。 用于交替驱动像素的矩阵寻址方法。 图像的帧周期通过在多个块周期的时间序列上连续排序形成，每个块周期由作为用于对一个像素电压的时间序列应用定时的连续排序的前半部分组成的第一半块组成 或更多的行电极被设置为一个极性，第二半块是用于对要被提供有另一极性的一个或多个行电极的像素电压的时间序列应用定时连续排序的周期。 在第一半块中选择偶数行电极和奇数行电极在显示屏上的排列顺序。 在下半部分中选择与空间相邻的那些。 在一个帧周期期间，前半个块中的行电极选择顺序和第二半块中的行电极选择顺序分别与在另一个帧周期期间的对应的半块中的阶数不同，以便减轻块周期 -base视觉伪影。