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公开(公告)号：US09124227B2
公开(公告)日：2015-09-01
申请号：US13622170
申请日：2012-09-18
申请人： Minsheng Wang , Iuri Mehr , Jungwoo Song , Vinay Chandrasekhar
发明人： Minsheng Wang , Iuri Mehr , Jungwoo Song , Vinay Chandrasekhar
CPC分类号： H03F1/34 , H03F1/3211 , H03F3/187 , H03F3/45475 , H03F2203/45521 , H03G3/3005
摘要： Systems and methods are disclosed to provide automatic power control for a driver circuit. Embodiments disclosed herein enable a driver circuit to automatically decrease the gain of amplified input signals when output power exceeds a threshold. Further, embodiments disclosed herein enable a driver circuit to automatically increase the gain of amplified input signals when battery supply voltage drops to avoid unwanted output signal distortion. By using reference signals for battery power and amplified signal input, the amplifiers of the driver circuit can be automatically adjusted until an equilibrium is reached.
摘要翻译： 公开了系统和方法来为驱动器电路提供自动功率控制。 当输出功率超过阈值时，本文公开的实施例使得驱动器电路能够自动降低放大的输入信号的增益。 此外，本文公开的实施例使得当电池电源电压下降时，驱动器电路自动地增加放大的输入信号的增益，以避免不期望的输出信号失真。 通过使用电池电源和放大信号输入的参考信号，可以自动调节驱动电路的放大器，直到达到平衡。
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公开(公告)号：US20140079246A1
公开(公告)日：2014-03-20
申请号：US13622170
申请日：2012-09-18
申请人： Minsheng Wang , Iuri Mehr , Jungwoo Song , Vinay Chandrasekhar
发明人： Minsheng Wang , Iuri Mehr , Jungwoo Song , Vinay Chandrasekhar
CPC分类号： H03F1/34 , H03F1/3211 , H03F3/187 , H03F3/45475 , H03F2203/45521 , H03G3/3005
摘要： Systems and methods are disclosed to provide automatic power control for a driver circuit. Embodiments disclosed herein enable a driver circuit to automatically decrease the gain of amplified input signals when output power exceeds a threshold. Further, embodiments disclosed herein enable a driver circuit to automatically increase the gain of amplified input signals when battery supply voltage drops to avoid unwanted output signal distortion. By using reference signals for battery power and amplified signal input, the amplifiers of the driver circuit can be automatically adjusted until an equilibrium is reached.
摘要翻译： 公开了系统和方法来为驱动器电路提供自动功率控制。 当输出功率超过阈值时，本文公开的实施例使得驱动器电路能够自动降低放大的输入信号的增益。 此外，本文公开的实施例使得当电池电源电压下降时，驱动器电路自动地增加放大的输入信号的增益，以避免不期望的输出信号失真。 通过使用电池电源和放大信号输入的参考信号，可以自动调节驱动电路的放大器，直到达到平衡。
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3.发明授权公开(公告)号：US07026970B2
公开(公告)日：2006-04-11
申请号：US11031071
申请日：2005-01-10
申请人： Minsheng Wang , Jungwoo Song
发明人： Minsheng Wang , Jungwoo Song
IPC分类号： H03M3/00
CPC分类号： H03M7/3042
摘要： Provided are a system and method for implementing a multirate analog finite impulse response (FIR) filter. A system of the present invention includes a modulator having a first adder and a quantizer. The first adder includes an output port, and the quantizer includes (i) an input port coupled to the first adder output port and (ii) a quantizer output port. A second adder is also included, having one input port coupled to the first adder output port and another input port coupled to the quantizer output port. Also included are at least two two-unit delays, a first of the two-unit delays having an input port coupled to an output port of the second adder, and an output port coupled to an input port of the second of the two-unit delays. An output port of the second two-unit delays is coupled to a first input port of the first adder.
摘要翻译： 提供了一种用于实现多速率模拟有限脉冲响应（FIR）滤波器的系统和方法。 本发明的系统包括具有第一加法器和量化器的调制器。 第一加法器包括输出端口，并且量化器包括（i）耦合到第一加法器输出端口的输入端口和（ii）量化器输出端口。 还包括第二加法器，具有耦合到第一加法器输出端口的一个输入端口和耦合到量化器输出端口的另一个输入端口。 还包括至少两个两单元延迟，两单元延迟中的第一个具有耦合到第二加法器的输出端口的输入端口，以及耦合到两单元中的第二个单元的输入端口的输出端口 延误 第二两单元延迟的输出端口耦合到第一加法器的第一输入端口。
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4.发明授权公开(公告)号：US08237496B2
公开(公告)日：2012-08-07
申请号：US12804834
申请日：2010-07-29
申请人： Xicheng Jiang , Jungwoo Song , Minsheng Wang , Todd L. Brooks
发明人： Xicheng Jiang , Jungwoo Song , Minsheng Wang , Todd L. Brooks
IPC分类号： H03F3/38
CPC分类号： H03F3/217
摘要： Disclosed is a switching amplifier having an enhanced supply rejection. The switching amplifier comprises a digital modulator that provides a modulated signal. The switching amplifier further comprises a closed-loop analog driver that is coupled to the digital modulator. As disclosed, the closed-loop analog driver is configured to re-modulate a modulation signal that corresponds to the modulated signal. An output stage of the switching amplifier is driven by the re-modulated signal, thereby providing enhanced supply rejection. In one embodiment, the modulated signal is produced by a digital pulse-width modulator (PWM) circuit of a Class-D amplifier, and has a pulse rate substantially less than a clock rate of the digital PWM circuit. In one embodiment, the switching amplifier is implemented as an audio amplifier in a mobile communication device such as a cellular telephone.
摘要翻译： 公开了具有增强的电源抑制的开关放大器。 开关放大器包括提供调制信号的数字调制器。 开关放大器还包括耦合到数字调制器的闭环模拟驱动器。 如所公开的，闭环模拟驱动器被配置为重新调制对应于调制信号的调制信号。 开关放大器的输出级由再调制信号驱动，从而提供增强的电源抑制。 在一个实施例中，调制信号由D类放大器的数字脉冲宽度调制器（PWM）电路产生，并且具有基本上小于数字PWM电路的时钟速率的脉冲速率。 在一个实施例中，开关放大器被实现为诸如蜂窝电话的移动通信设备中的音频放大器。
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5.发明申请公开(公告)号：US20050179574A1
公开(公告)日：2005-08-18
申请号：US11031071
申请日：2005-01-10
申请人： Minsheng Wang , Jungwoo Song
发明人： Minsheng Wang , Jungwoo Song
CPC分类号： H03M7/3042
摘要： Provided are a system and method for implementing a multirate analog finite impulse response (FIR) filter. A system of the present invention includes a modulator having a first adder and a quantizer. The first adder includes an output port, and the quantizer includes (i) an input port coupled to the first adder output port and (ii) a quantizer output port. A second adder is also included, having one input port coupled to the first adder output port and another input port coupled to the quantizer output port. Also included are at least two two-unit delays, a first of the two-unit delays having an input port coupled to an output port of the second adder, and an output port coupled to an input port of the second of the two-unit delays. An output port of the second two-unit delays is coupled to a first input port of the first adder.
摘要翻译： 提供了一种用于实现多速率模拟有限脉冲响应（FIR）滤波器的系统和方法。 本发明的系统包括具有第一加法器和量化器的调制器。 第一加法器包括输出端口，并且量化器包括（i）耦合到第一加法器输出端口的输入端口和（ii）量化器输出端口。 还包括第二加法器，具有耦合到第一加法器输出端口的一个输入端口和耦合到量化器输出端口的另一个输入端口。 还包括至少两个两单元延迟，两单元延迟中的第一个具有耦合到第二加法器的输出端口的输入端口，以及耦合到两单元中的第二个单元的输入端口的输出端口 延误 第二两单元延迟的输出端口耦合到第一加法器的第一输入端口。
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6.发明授权Closed-loop class-D amplifier with modulated reference signal and related method 有权具有调制参考信号的闭环D类放大器及相关方法公开(公告)号：US08212612B2
公开(公告)日：2012-07-03
申请号：US12804318
申请日：2010-07-19
申请人： Jungwoo Song , Xicheng Jiang , Minsheng Wang , Todd L. Brooks
发明人： Jungwoo Song , Xicheng Jiang , Minsheng Wang , Todd L. Brooks
CPC分类号： H03F3/217
摘要： Disclosed is a closed-loop class-D amplifier circuit including a modulated reference signal generator that provides a modulated reference signal in a feed-forward path, where the reference signal is modulated corresponding to an input signal. The closed-loop class-D amplifier circuit further includes a comparator to generate a control signal based on a comparison of the modulated reference signal and a correction signal, which in turn is produced by filtering a combination of the input signal and a feedback signal. The closed-loop class-D amplifier circuit also includes a pulse generator to generate a pulse-width-modulated signal to drive an output stage of the closed-loop class-D amplifier based on the control signal.
摘要翻译： 公开了一种闭环D类放大器电路，其包括在前馈路径中提供调制参考信号的调制参考信号发生器，其中参考信号根据输入信号被调制。 闭环D类放大器电路还包括比较器，用于基于调制参考信号和校正信号的比较产生控制信号，校正信号又通过滤波输入信号和反馈信号的组合来产生。 闭环D类放大器电路还包括脉冲发生器，以产生脉冲宽度调制信号，以根据控制信号驱动闭环D类放大器的输出级。
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公开(公告)号：US20120025910A1
公开(公告)日：2012-02-02
申请号：US12804834
申请日：2010-07-29
申请人： Xicheng Jiang , Jungwoo Song , Minsheng Wang , Todd L. Brooks
发明人： Xicheng Jiang , Jungwoo Song , Minsheng Wang , Todd L. Brooks
IPC分类号： H03F3/217
CPC分类号： H03F3/217
摘要： Disclosed is a switching amplifier having an enhanced supply rejection. The switching amplifier comprises a digital modulator that provides a modulated signal. The switching amplifier further comprises a closed-loop analog driver that is coupled to the digital modulator. As disclosed, the closed-loop analog driver is configured to re-modulate a modulation signal that corresponds to the modulated signal. An output stage of the switching amplifier is driven by the re-modulated signal, thereby providing enhanced supply rejection. In one embodiment, the modulated signal is produced by a digital pulse-width modulator (PWM) circuit of a Class-D amplifier, and has a pulse rate substantially less than a clock rate of the digital PWM circuit. In one embodiment, the switching amplifier is implemented as an audio amplifier in a mobile communication device such as a cellular telephone.
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8.发明申请Closed-loop class-d amplifier with modulated reference signal and related method 有权具有调制参考信号的闭环D类放大器及相关方法公开(公告)号：US20120013402A1
公开(公告)日：2012-01-19
申请号：US12804318
申请日：2010-07-19
申请人： Jungwoo Song , Xicheng Jiang , Minsheng Wang , Todd L. Brooks
发明人： Jungwoo Song , Xicheng Jiang , Minsheng Wang , Todd L. Brooks
IPC分类号： H03F1/00
CPC分类号： H03F3/217
摘要： Disclosed is a closed-loop class-D amplifier circuit including a modulated reference signal generator that provides a modulated reference signal in a feed-forward path, where the reference signal is modulated corresponding to an input signal. The closed-loop class-D amplifier circuit further includes a comparator to generate a control signal based on a comparison of the modulated reference signal and a correction signal, which in turn is produced by filtering a combination of the input signal and a feedback signal. The closed-loop class-D amplifier circuit also includes a pulse generator to generate a pulse-width-modulated signal to drive an output stage of the closed-loop class-D amplifier based on the control signal.
摘要翻译： 公开了一种闭环D类放大器电路，其包括在前馈路径中提供调制参考信号的调制参考信号发生器，其中参考信号根据输入信号被调制。 闭环D类放大器电路还包括比较器，用于基于调制参考信号和校正信号的比较产生控制信号，校正信号又通过滤波输入信号和反馈信号的组合来产生。 闭环D类放大器电路还包括脉冲发生器，以产生脉冲宽度调制信号，以根据控制信号驱动闭环D类放大器的输出级。
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公开(公告)号：US06856267B1
公开(公告)日：2005-02-15
申请号：US10778193
申请日：2004-02-17
申请人： Minsheng Wang , Jungwoo Song
发明人： Minsheng Wang , Jungwoo Song
CPC分类号： H03M7/3042
摘要： Provided are a system and method for implementing a multirate analog finite impulse response (FIR) filter. A system of the present invention includes a modulator having a first adder and a quantizer. The first adder includes an output port, and the quantizer includes (i) an input port coupled to the first adder output port and (ii) a quantizer output port. A second adder is also included, having one input port coupled to the first adder output port and another input port coupled to the quantizer output port. Also included are at least two two-unit delays, a first of the two-unit delays having an input port coupled to an output port of the second adder, and an output port coupled to an input port of the second of the two-unit delays. An output port of the second two-unit delays is coupled to a first input port of the first adder.
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公开(公告)号：US11533493B2
公开(公告)日：2022-12-20
申请号：US17158102
申请日：2021-01-26
申请人： Minsheng Wang , Maojian Xiang , Xiaojun Liu
发明人： Minsheng Wang , Maojian Xiang , Xiaojun Liu
IPC分类号： H04N19/176 , H04N19/124
摘要： A video encoding method is provided in the present invention. The method includes: determining a range of interest ROI in an ith frame, wherein the ROI comprises at least one ROI macroblock; extracting characteristic information of the at least one ROI macroblock, wherein the characteristic information comprises location information and type information of the at least one ROI macroblock; determining a quantization parameter QP corresponding to each of the at least one ROI macroblock; encoding the characteristic information of the at least one ROI macroblock according to the determined QP corresponding to each ROI macroblock, to obtain an ROI characteristic stream of the ith frame; and adding, to a video stream of the ith frame, the QP corresponding to each ROI macroblock and the ROI characteristic stream of the ith frame, to perform sending, wherein the video stream of the ith frame is obtained by encoding the ROI and a non-ROI comprised in the ith frame.
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