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公开(公告)号：US06728835B1
公开(公告)日：2004-04-27
申请号：US09650730
申请日：2000-08-30
IPC分类号： G06F1200
CPC分类号： G06F12/0897 , G06F12/0888 , G06F12/126
摘要： An apparatus for and method of improving the efficiency of a level two cache memory. In response to a level one cache miss, a request is made to the level two cache. A signal sent with the request identifies when the requester does not anticipate a near term subsequent use for the requested data element. If a level two cache hit occurs, the requested data element is marked as least recently used in response to the signal. If a level two cache miss occurs, a request is made to level three storage. When the level three storage request is honored, the requested data element is immediately flushed from the level two cache memory in response to the signal.
摘要翻译： 一种用于提高二级高速缓冲存储器的效率的装置和方法。 响应于一级缓存未命中，对二级缓存进行请求。 与该请求一起发送的信号标识何时请求者不期望对所请求的数据元素的近期使用。 如果发生二级缓存命中，则所请求的数据元素被标记为响应于该信号最近最少使用。 如果发生二级高速缓存未命中，则要求进行三级存储。 当三级存储请求被授予时，响应于该信号立即从二级高速缓冲存储器刷新所请求的数据元素。
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公开(公告)号：US07260677B1
公开(公告)日：2007-08-21
申请号：US10620515
申请日：2003-07-16
IPC分类号： G06F12/06
CPC分类号： G06F12/0817 , G06F12/084
摘要： A memory control system and method is disclosed. In one embodiment, a first memory is coupled to one or more additional memories. The first memory receives requests for data that are completed by retrieving the data from the first memory and/or the one or more additional memories. The manner in which this data is retrieved is determined by the state of programmable control indicators. In one mode of operation, a reference is made to the first memory to retrieve the data. If it is later determined from tag information stored by the first memory that the one or more additional memories must be accessed to fulfill the request, the necessary additional memory references are initiated. In another mode of operation, references to the one or more additional memories are initiated irrespective of whether these references are required. The operating mode may be selected to optimize system efficiency.
摘要翻译： 公开了一种存储器控制系统和方法。 在一个实施例中，第一存储器耦合到一个或多个附加存储器。 第一存储器通过从第一存储器和/或一个或多个附加存储器检索数据来接收对完成的数据的请求。 检索数据的方式由可编程控制指示灯的状态决定。 在一种操作模式中，引用第一存储器来检索数据。 如果随后由第一存储器存储的标签信息确定必须访问一个或多个附加存储器以满足请求，则启动必要的附加存储器引用。 在另一种操作模式中，无论是否需要这些引用，都会启动对一个或多个附加存储器的引用。 可以选择操作模式以优化系统效率。
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3.发明授权Multi-processor data processing system with control for granting multiple storage locks in parallel and parallel lock priority and second level cache priority queues 失效多处理器数据处理系统具有并行授予多个存储锁的并行锁定优先级和二级缓存优先级队列的控制
公开(公告)号：US5678026A
公开(公告)日：1997-10-14
申请号：US579896
申请日：1995-12-28
IPC分类号： G06F9/46 , G06F13/18 , G06F13/362
摘要： A storage lock apparatus for a multiprocessor data processing system. The storage lock apparatus includes control for granting locks to different selectable portions of storage in parallel. In addition, acknowledgment from a remote lock controller is not required for a processor to obtain a lock on an address, even if the address for which the lock was requested is not local relative to the processor. Parallel priority queues are employed for parallel handling of storage lock functions and general storage operations, thereby reducing contention for priority between storage lock operations and general storage operations where there are no addressing conflicts.
摘要翻译： 一种用于多处理器数据处理系统的存储锁定装置。 存储锁定装置包括用于将锁定并行地存储到不同可选择的存储部分的控制。 此外，处理器不需要来自远程锁定控制器的确认来获得地址上的锁定，即使所请求的锁定的地址相对于处理器不是局部的。 并行优先级队列用于并行处理存储锁定功能和一般存储操作，从而减少存储锁定操作与无寻址冲突的一般存储操作之间的优先级争用。
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公开(公告)号：US06973548B1
公开(公告)日：2005-12-06
申请号：US10600205
申请日：2003-06-20
CPC分类号： G06F12/0831 , G06F12/0828
摘要： A dual-channel memory system and accompanying coherency mechanism is disclosed. The memory includes both a request and a response channel. The memory provides data to a requester such as an instruction processor via the response channel. If this data is provided for update purposes, other read-only copies of the data must be invalidated. This invalidation may occur after the data is provided for update purposes, and is accomplished by issuing one or more invalidation requests via one of the memory request or the response channel. Memory coherency is maintained by preventing a requester from storing any data back to memory until all invalidation activities that may be directly or indirectly associated with that data have been completed.
摘要翻译： 公开了一种双通道存储器系统和附带的一致性机制。 存储器包括请求和响应信道。 存储器通过响应信道向诸如指令处理器的请求者提供数据。 如果提供此数据用于更新目的，数据的其他只读副本必须无效。 在为更新目的提供数据之后可能发生这种无效，并且通过经由存储器请求或响应信道之一发出一个或多个无效请求来实现。 通过防止请求者将任何数据存储回存储器，直到所有可能与该数据直接或间接相关联的无效活动已经完成来维持内存一致性。
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5.发明授权System and method for performing error recovery in a data processing system having multiple processing partitions 有权用于在具有多个处理分区的数据处理系统中执行错误恢复的系统和方法公开(公告)号：US07343515B1
公开(公告)日：2008-03-11
申请号：US10954842
申请日：2004-09-30
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/0712 , G06F11/0724
摘要： A system and method is disclosed for performing error recovery in a data processing system that supports multiple processing partitions. One or more processors and I/O modules, as well as a portion of the address space of a main memory, is allocated to each partition. In this type of configuration, requests generated by units of multiple partitions are processed by the same queue and state logic of the main memory. When a failure occurs within one processing partition, one or more units are identified as being directly affected by the fault. All requests and responses from, and to, the affected units, as well as any logical residue of these requests and responses are removed from the shared memory queue and state logic in a manner that allows the other partition to continue issuing requests and responses to the memory in a normal manner that does not involve recovery operations.
摘要翻译： 公开了一种用于在支持多个处理分区的数据处理系统中执行错误恢复的系统和方法。 一个或多个处理器和I / O模块以及主存储器的地址空间的一部分被分配给每个分区。 在这种类型的配置中，由多个分区的单元生成的请求由主存储器的相同队列和状态逻辑处理。 当在一个处理分区内发生故障时，一个或多个单元被识别为直接受故障影响。 受影响单位的所有请求和响应以及这些请求和响应的任何逻辑残差都以共享内存队列和状态逻辑的方式被删除，从而允许其他分区继续发出请求和响应 记忆以不涉及恢复操作的正常方式。
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6.发明授权公开(公告)号：US07167955B1
公开(公告)日：2007-01-23
申请号：US10745372
申请日：2003-12-23
IPC分类号： G06F12/00
CPC分类号： G06F12/0817 , G06F11/1008 , G06F2212/1032
摘要： A system and method for testing and/or initializing a Directory Store in a directory-based coherent memory. In one illustrative embodiment, the directory-based coherent memory includes a Main Store for storing a number of data entries, a Directory Store for storing the directory state for at least some of the data entries in the Main Store, and a next state block for determining a next directory state for a requested data entry in response to a memory request. To provide access to the Directory Store, and in one illustrative embodiment, a selector is provided for selecting either the next directory state value provided by the next state block or another predetermined value. The other predetermined value may be, for example, a fixed data pattern, a variable data pattern, a specified value, or any other value suitable for initializing and/or testing the Directory Store. The output of the selector may be written to the Directory Store.
摘要翻译： 用于在基于目录的连贯内存中测试和/或初始化目录存储的系统和方法。 在一个说明性实施例中，基于目录的相干存储器包括用于存储多个数据条目的主存储器，用于存储主存储器中的至少一些数据条目的目录状态的目录存储器，以及下一个状态块 响应于存储器请求确定所请求的数据条目的下一目录状态。 为了提供对目录存储的访问，并且在一个说明性实施例中，提供了选择器，用于选择由下一个状态块提供的下一个目录状态值或另一个预定值。 另一个预定值可以是例如固定数据模式，可变数据模式，指定值或适用于初始化和/或测试目录库的任何其他值。 选择器的输出可能会写入目录存储。
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7.发明授权System and method for fault handling and recovery in a multi-processing system having hardware resources shared between multiple partitions 有权具有在多个分区之间共享的硬件资源的多处理系统中的故障处理和恢复的系统和方法公开(公告)号：US06594785B1
公开(公告)日：2003-07-15
申请号：US09561270
申请日：2000-04-28
申请人： Roger L. Gilbertson , Mitchell A. Bauman , Penny L. Svenkeson , James L. DePenning , Michael L. Haupt , Donald Kalvestrand , Daniel S. Tokoly , Frederick G. Fellenser , Maria A. Liedman
发明人： Roger L. Gilbertson , Mitchell A. Bauman , Penny L. Svenkeson , James L. DePenning , Michael L. Haupt , Donald Kalvestrand , Daniel S. Tokoly , Frederick G. Fellenser , Maria A. Liedman
IPC分类号： H02H305
CPC分类号： G06F11/0772 , G06F11/0712 , G06F11/0724 , G06F11/0793
摘要： Poisoning of specific memory locations as a process when a part of a multiprocessor computer system becomes faulty leads to ability to isolate specific data owned by individual failing units even in a shared memory area. Also continuous processing by non-failing units is allowable. A support processor handles non-immediate problems and allows resetting of memory locations formerly owned by failed units.
摘要翻译： 当多处理器计算机系统的一部分变得有故障时，将特定存储器位置中毒作为过程导致即使在共享存储器区域中也能够分离由单个故障单元拥有的特定数据的能力。 也可以由非故障单元进行连续处理。 支持处理器处理非直接问题，并允许重置以前由故障单元拥有的存储器位置。
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8.发明授权Directory-based cache coherency system supporting multiple instruction processor and input/output caches 失效基于目录的高速缓存一致性系统支持多指令处理器和输入/输出缓存公开(公告)号：US06587931B1
公开(公告)日：2003-07-01
申请号：US09001598
申请日：1997-12-31
IPC分类号： G06F1208
CPC分类号： G06F12/0817 , G06F12/0886 , G06F2212/621
摘要： A directory-based cache coherency system is disclosed for use in a data processing system having multiple Instruction Processors (IP) and multiple Input/Output (I/O) units coupled through a shared main memory. The system includes one or more IP cache memories, each coupled to one or more IPs and to the shared main memory for caching units of data referred to as cache lines. The system further includes one or more I/O memories within ones of the I/O units, each I/O memory being coupled to the shared main memory for storing cache lines retrieved from the shared main memory. Coherency is maintained through the use of a central directory which stores status for each of the cache lines in the system. The status indicates the identity of the IP caches and the I/O memories having valid copies of a given cache line, and further identifies a set of access privileges, that is, the cache line “state”, associated with the cache line. The cache line states are used to implement a state machine which tracks the cache lines and ensures only valid copies of are maintained within the memory system. According to another aspect of the system, the main memory performs continuous tracking and control functions for all cache lines residing in the IP caches. In contrast, the system maintains tracking and control functions for only predetermined cache lines provided to the I/O units so that system overhead may be reduced. The coherency system further supports multiple heterogeneous instruction processors which operate on cache lines of different sizes.
摘要翻译： 公开了一种基于目录的高速缓存一致性系统，用于具有通过共享主存储器耦合的多个指令处理器（IP）和多个输入/输出（I / O）单元的数据处理系统。 该系统包括一个或多个IP高速缓冲存储器，每个IP缓存存储器分别耦合到一个或多个IP和共享主存储器，用于高速缓存被称为高速缓存线的数据单元。 该系统还包括一个或多个I / O单元内的I / O存储器，每个I / O存储器耦合到共享主存储器，用于存储从共享主存储器检索的高速缓存线。 通过使用存储系统中每个缓存行的状态的中央目录来维护一致性。 该状态表示IP高速缓存和具有给定高速缓存行的有效副本的I / O存储器的身份，并进一步标识与高速缓存行相关联的一组访问权限，即高速缓存行“状态”。 高速缓存行状态用于实现跟踪高速缓存行的状态机，并且仅确保在存储器系统内维护的有效副本。 根据系统的另一方面，主存储器对驻留在IP高速缓存中的所有高速缓存行执行连续跟踪和控制功能。 相比之下，系统仅为提供给I / O单元的预定高速缓存行维护跟踪和控制功能，从而可以减少系统开销。 一致性系统还支持在不同大小的高速缓存线上运行的多个异构指令处理器。
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公开(公告)号：US06477620B1
公开(公告)日：2002-11-05
申请号：US09467190
申请日：1999-12-20
申请人： Mitchell A. Bauman , Roger L. Gilbertson , Donald R. Kalvestrand , Joseph S. Schibinger , Daniel S. Tokoly
发明人： Mitchell A. Bauman , Roger L. Gilbertson , Donald R. Kalvestrand , Joseph S. Schibinger , Daniel S. Tokoly
IPC分类号： G06F1208
CPC分类号： G06F12/0813 , G06F12/0811
摘要： A data by-pass system for a hierarchical, multi-level, memory is disclosed. The by-pass system provides by-pass interfaces between storage devices located at predetermined levels within the memory hierarchy. The hierarchical memory system of the preferred embodiment includes a main memory coupled to multiple first storage devices that each stores addressable portions of data signals retrieved from the main memory. To facilitate a more efficient transfer of data between the various storage devices in the memory system, at least one by-pass interface coupling associated ones of the first storage devices is provided. Data retrieved from a target one of the first storage devices in response to a main memory request can be routed to a different requesting one of the first storage devices via the by-pass system without requiring the use of the main memory data interfaces.
摘要翻译： 公开了一种用于分级，多级存储器的数据旁路系统。 旁路系统在位于存储器层级内的预定级别的存储设备之间提供旁路接口。 优选实施例的分级存储器系统包括耦合到多个第一存储设备的主存储器，每个存储器件存储从主存储器检索的数据信号的可寻址部分。 为了便于在存储器系统中的各种存储设备之间更有效地传输数据，提供了耦合相关联的第一存储设备的至少一个旁路接口。 可以响应于主存储器请求从第一存储设备中的目标一个检索的数据经由旁路系统路由到第一存储设备中的不同请求的一个，而不需要使用主存储器数据接口。
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公开(公告)号：US06356991B1
公开(公告)日：2002-03-12
申请号：US09001390
申请日：1997-12-31
IPC分类号： G06F1206
CPC分类号： G06F12/0607 , G06F12/0292
摘要： A programmable address translation system for a modular main memory is provided. The system is implemented using one or more General Register Arrays (GRAs), wherein each GRA performs logical-to-physical address translation for a predetermined address range within the system. Predetermined bits of a logical address are used to address a GRA associated with the logical address range. Data bits read from the GRA are then substituted for the predetermined bits of the logical address to form the physical address. In this manner, non-contiguous addressable banks of physical memory may be mapped to a selectable contiguous address range. By including within the GRA Address a number N of logical address bits used to address contiguous logical addresses, an address translation mechanism is provided which may be programmed to perform between 2-way and 2N-way address interleaving. Each GRA may be re-programmed dynamically to accommodate changing memory conditions as may occur, for example, when a range of memory is logically removed from a system because of errors. Furthermore, GRA reprogramming may occur while memory operations continue within other non-associated address ranges. Additionally, address interleaving may be selected for certain ones of the address ranges, whereas a non-interleaving scheme may be selected for other address ranges.
摘要翻译： 提供了一种用于模块化主存储器的可编程地址转换系统。 该系统使用一个或多个通用寄存器阵列（GRA）实现，其中每个GRA对系统内的预定地址范围进行逻辑到物理地址转换。 使用逻辑地址的预定比特来寻址与逻辑地址范围相关联的GRA。 然后将从GRA读取的数据位代替逻辑地址的预定位以形成物理地址。 以这种方式，物理存储器的不连续可寻址组可以被映射到可选择的相邻地址范围。 通过在GRA地址内包含用于寻址连续逻辑地址的N个逻辑地址位，提供地址转换机制，其可被编程为在2路和2N路地址交错之间执行。 可以动态地重新编程每个GRA以适应可能发生的变化的存储器条件，例如当由于错误而从系统逻辑地移除存储器的范围时。 此外，当存储器操作在其他非关联地址范围内继续时，可能会发生GRA重新编程。 另外，可以针对某些地址范围来选择地址交织，而对于其他地址范围可以选择非交织方案。
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