公开(公告)号：US07260677B1

公开(公告)日：2007-08-21

申请号：US10620515

申请日：2003-07-16

申请人： Kelvin S. Vartti ,  Ross M. Weber ,  Mitchell A. Bauman

发明人： Kelvin S. Vartti ,  Ross M. Weber ,  Mitchell A. Bauman

IPC分类号： G06F12/06

CPC分类号： G06F12/0817 ,  G06F12/084

摘要： A memory control system and method is disclosed. In one embodiment, a first memory is coupled to one or more additional memories. The first memory receives requests for data that are completed by retrieving the data from the first memory and/or the one or more additional memories. The manner in which this data is retrieved is determined by the state of programmable control indicators. In one mode of operation, a reference is made to the first memory to retrieve the data. If it is later determined from tag information stored by the first memory that the one or more additional memories must be accessed to fulfill the request, the necessary additional memory references are initiated. In another mode of operation, references to the one or more additional memories are initiated irrespective of whether these references are required. The operating mode may be selected to optimize system efficiency.

摘要翻译： 公开了一种存储器控制系统和方法。 在一个实施例中，第一存储器耦合到一个或多个附加存储器。 第一存储器通过从第一存储器和/或一个或多个附加存储器检索数据来接收对完成的数据的请求。 检索数据的方式由可编程控制指示灯的状态决定。 在一种操作模式中，引用第一存储器来检索数据。 如果随后由第一存储器存储的标签信息确定必须访问一个或多个附加存储器以满足请求，则启动必要的附加存储器引用。 在另一种操作模式中，无论是否需要这些引用，都会启动对一个或多个附加存储器的引用。 可以选择操作模式以优化系统效率。

公开(公告)号：US06973548B1

公开(公告)日：2005-12-06

申请号：US10600205

申请日：2003-06-20

申请人： Kelvin S. Vartti ,  Ross M. Weber ,  Mitchell A. Bauman ,  Ronald G. Arnold

发明人： Kelvin S. Vartti ,  Ross M. Weber ,  Mitchell A. Bauman ,  Ronald G. Arnold

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0831 ,  G06F12/0828

摘要： A dual-channel memory system and accompanying coherency mechanism is disclosed. The memory includes both a request and a response channel. The memory provides data to a requester such as an instruction processor via the response channel. If this data is provided for update purposes, other read-only copies of the data must be invalidated. This invalidation may occur after the data is provided for update purposes, and is accomplished by issuing one or more invalidation requests via one of the memory request or the response channel. Memory coherency is maintained by preventing a requester from storing any data back to memory until all invalidation activities that may be directly or indirectly associated with that data have been completed.

摘要翻译： 公开了一种双通道存储器系统和附带的一致性机制。 存储器包括请求和响应信道。 存储器通过响应信道向诸如指令处理器的请求者提供数据。 如果提供此数据用于更新目的，数据的其他只读副本必须无效。 在为更新目的提供数据之后可能发生这种无效，并且通过经由存储器请求或响应信道之一发出一个或多个无效请求来实现。 通过防止请求者将任何数据存储回存储器，直到所有可能与该数据直接或间接相关联的无效活动已经完成来维持内存一致性。

公开(公告)号：US07533223B1

公开(公告)日：2009-05-12

申请号：US11784238

申请日：2007-04-06

申请人： Kelvin S. Vartti ,  Ross M. Weber

发明人： Kelvin S. Vartti ,  Ross M. Weber

IPC分类号： G06F12/00

CPC分类号： G06F12/0828 ,  G06F13/1642

摘要： A system and method are provided for tracking memory requests within a data processing system. The system includes a request tracking circuit that is coupled to receive requests for data from multiple processors. Multiple pending requests to the same memory address are tracked using a linked list. Only the oldest pending one of these multiple requests is issued to the memory. When data is returned from the memory, the requests are processed in an order determined by the linked list. That is, the data is provided to a processor associated with the oldest request. Thereafter, the data is retrieved and provided to the processor associated with the next request, and so on. A request issued by the memory soliciting the return of the data to the memory may also be added to the linked list to be processed in the foregoing manner.

摘要翻译： 提供了一种系统和方法来跟踪数据处理系统内的存储器请求。 该系统包括一个请求跟踪电路，该电路被耦合以接收来自多个处理器的数据请求。 使用链表跟踪对同一内存地址的多个挂起请求。 只有这些多个请求中的最旧的等待一个发出到内存。 当从存储器返回数据时，以由链表确定的顺序处理请求。 也就是说，将数据提供给与最早请求相关联的处理器。 此后，数据被检索并提供给与下一请求相关联的处理器，等等。 由存储器发出的请求发出的请求也可以以上述方式被添加到链接列表中以被处理。

公开(公告)号：US07299311B1

公开(公告)日：2007-11-20

申请号：US11321508

申请日：2005-12-29

申请人： Chad M. Sepeda ,  Kelvin S. Vartti ,  Ross M. Weber

发明人： Chad M. Sepeda ,  Kelvin S. Vartti ,  Ross M. Weber

IPC分类号： G06F13/18

CPC分类号： G06F13/364

摘要： A system and method for arbitrating for access to a resource group between agents according to a respective programmable weight for each agent. For each agent, a programmable mapping module selectively couples a respective arbitration handshake signal of the agent to one or more arbitration ports, and the number of the coupled arbitration ports for the agent is the respective programmable weight. A selection module selects one of the arbitration ports in response to a priority ranking of the arbitration ports, and access to the resource group is granted to the agent that has the respective arbitration handshake signal that is selectively coupled by the programmable mapping module to the selected arbitration port. A ranking module provides the priority ranking of the arbitration ports and updates the priority ranking in response to the selection module selecting the selected arbitration port.

摘要翻译： 一种用于根据每个代理的相应可编程权重仲裁对代理之间的资源组的访问的系统和方法。 对于每个代理，可编程映射模块选择性地将代理的相应仲裁握手信号耦合到一个或多个仲裁端口，并且代理的耦合仲裁端口的数量是相应的可编程权重。 选择模块响应于仲裁端口的优先级排序选择一个仲裁端口，并且向具有相应的仲裁握手信号的代理授予对资源组的访问，所述仲裁握手信号由可编程映射模块选择性地耦合到所选择的 仲裁口岸 排序模块提供仲裁端口的优先级排序，并响应于选择模块选择所选仲裁端口而更新优先级排序。

公开(公告)号：US07496715B1

公开(公告)日：2009-02-24

申请号：US10620406

申请日：2003-07-16

申请人： Kelvin S. Vartti ,  Ross M. Weber

发明人： Kelvin S. Vartti ,  Ross M. Weber

IPC分类号： G06F12/08

CPC分类号： G06F12/0888 ,  G06F12/0811 ,  G06F12/0817 ,  G06F12/121 ,  G06F2212/1021 ,  G06F2212/601

摘要： A memory control system and method is disclosed. The system includes cache tag logic and an optional cache coupled to a main memory. If available, the cache retains a subset of the data stored within the main memory. This subset is selected by programmable control indicators. These indicators further control which data will be recorded by the tag logic. The indicators may select the sub-sets based on which type of memory request results in the return of data from the main memory to the cache, for example. Alternatively, or in addition, these indicators may specify the identity of a requester, a memory response type, or a storage mode to control the selection of the sub-sets of data stored within the cache and recorded by the tag logic. In one embodiment, data may be tracked by the cache tag logic but not stored within the cache itself.

摘要翻译： 公开了一种存储器控制系统和方法。 该系统包括高速缓存标签逻辑和耦合到主存储器的可选缓存。 如果可用，缓存保留存储在主存储器内的数据的子集。 该子集由可编程控制指示器选择。 这些指示器进一步控制标签逻辑将记录哪些数据。 指示符可以基于哪种类型的存储器请求导致将数据从主存储器返回到高速缓存而选择子集。 或者或另外，这些指示符可以指定请求者的身份，存储器响应类型或存储模式，以控制存储在高速缓存内并由标签逻辑记录的数据子集的选择。 在一个实施例中，数据可以被高速缓存标签逻辑跟踪，但是不存储在高速缓存本身中。

公开(公告)号：US07222222B1

公开(公告)日：2007-05-22

申请号：US10601030

申请日：2003-06-20

申请人： Kelvin S. Vartti ,  Ross M. Weber

发明人： Kelvin S. Vartti ,  Ross M. Weber

IPC分类号： G06F12/00

CPC分类号： G06F12/0828 ,  G06F13/1642

摘要： A system and method are provided for tracking memory requests within a data processing system. The system includes a request tracking circuit that is coupled to receive requests for data from multiple processors. Multiple pending requests to the same memory address are tracked using a linked list. Only the oldest pending one of these multiple requests is issued to the memory. When data is returned from the memory, the requests are processed in an order determined by the linked list. That is, the data is provided to a processor associated with the oldest request. Thereafter, the data is retrieved and provided to the processor associated with the next request, and so on. A request issued by the memory soliciting the return of the data to the memory may also be added to the linked list to be processed in the foregoing manner.

摘要翻译： 提供了一种用于跟踪数据处理系统内的存储器请求的系统和方法。 该系统包括一个请求跟踪电路，该电路被耦合以接收来自多个处理器的数据请求。 使用链表跟踪对同一内存地址的多个挂起请求。 只有这些多个请求中的最旧的等待一个发出到内存。 当从存储器返回数据时，以由链表确定的顺序处理请求。 也就是说，将数据提供给与最早请求相关联的处理器。 此后，数据被检索并提供给与下一请求相关联的处理器，等等。 由存储器发出的请求发出的请求也可以以上述方式被添加到链接列表中以被处理。

公开(公告)号：US09177089B2

公开(公告)日：2015-11-03

申请号：US14474280

申请日：2014-09-01

申请人： Ziyad E. Hanna ,  Per Anders M. Franzen ,  Ross M. Weber ,  Habeeb A. Farah ,  Rajeev K. Ranjan

发明人： Ziyad E. Hanna ,  Per Anders M. Franzen ,  Ross M. Weber ,  Habeeb A. Farah ,  Rajeev K. Ranjan

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/504

摘要： A computer-implemented method and non-transitory computer readable medium for circuit design verification. Formal verification is performed on a circuit design to prove a correctness of a property of the circuit design. The circuit design has a cone of influence representing a portion of the circuit design capable of affecting signals of the property. A proof core of the circuit design is identified, the proof core being a portion of the cone of influence that is sufficient to prove the correctness of the property. A coverage metric is generated that is indicative of a level of formal verification coverage provided by the property based on the proof core of the circuit design.

摘要翻译： 一种用于电路设计验证的计算机实现的方法和非暂时性计算机可读介质。 对电路设计进行正式验证，以证明电路设计的属性的正确性。 电路设计具有代表电路设计能够影响该特性的信号的一部分的影响锥。 识别电路设计的核心，防爆核心是足以证明属性正确性的影响力的一部分。 产生一个覆盖度量，其指示由基于电路设计的验证核心的属性提供的形式验证覆盖水平。

公开(公告)号：US20150135150A1

公开(公告)日：2015-05-14

申请号：US14474280

申请日：2014-09-01

申请人： Ziyad E. Hanna ,  Per Anders M. Franzen ,  Ross M. Weber ,  Habeeb A. Farah ,  Rajeev K. Ranjan

发明人： Ziyad E. Hanna ,  Per Anders M. Franzen ,  Ross M. Weber ,  Habeeb A. Farah ,  Rajeev K. Ranjan

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/504

摘要： A computer-implemented method and non-transitory computer readable medium for circuit design verification. Formal verification is performed on a circuit design to prove a correctness of a property of the circuit design. The circuit design has a cone of influence representing a portion of the circuit design capable of affecting signals of the property. A proof core of the circuit design is identified, the proof core being a portion of the cone of influence that is sufficient to prove the correctness of the property. A coverage metric is generated that is indicative of a level of formal verification coverage provided by the property based on the proof core of the circuit design.

摘要翻译： 一种用于电路设计验证的计算机实现的方法和非暂时性计算机可读介质。 对电路设计进行正式验证，以证明电路设计的属性的正确性。 电路设计具有代表电路设计能够影响该特性的信号的一部分的影响锥。 识别电路设计的核心，防爆核心是足以证明属性正确性的影响力的一部分。 产生一个覆盖度量，其指示由基于电路设计的验证核心的属性提供的形式验证覆盖水平。

公开(公告)号：US07895379B2

公开(公告)日：2011-02-22

申请号：US12342213

申请日：2008-12-23

申请人： Ross M. Weber ,  David R. Spatafore

发明人： Ross M. Weber ,  David R. Spatafore

IPC分类号： G06F13/00 ,  G06F7/38

CPC分类号： G06F13/4027

摘要： Control logic of a node controller receives an input vector and produces an output vector. The control logic includes a plurality of tied control store entries including hard-coded logic to identify unique values of the input vector and to produce the output vector from a hard-coded output vector when the input vector is identified and when the tied control store is enabled. The control logic also includes a plurality of spare control store entries including programmable logic configurable to identify values of the input vector and to produce the output vector from a programmable output vector when the input vector is identified and when the spare control store is enabled. One of the spare control store entries that is configured to identify a value of the input vector that none of the tied control store entries that are enabled by the entry-enables register are configured to identify is enabled.

摘要翻译： 节点控制器的控制逻辑接收输入向量并产生输出向量。 控制逻辑包括多个连接的控制存储条目，包括用于识别输入向量的唯一值的硬编码逻辑，并且当识别输入向量时以及当绑定的控制存储器是 启用 控制逻辑还包括多个备用控制存储条目，其包括可配置为识别输入向量的值的可编程逻辑，并且当识别输入向量时以及当备用控制存储器被使能时，从可编程输出向量产生输出向量。 配置为标识输入向量的值之一的备用控制存储条目之一是启用由条目启用寄存器启用的绑定控制存储条目中的任何一个。

公开(公告)号：US20100161866A1

公开(公告)日：2010-06-24

申请号：US12342213

申请日：2008-12-23

申请人： Ross M. Weber ,  David R. Spatafore

发明人： Ross M. Weber ,  David R. Spatafore

IPC分类号： G06F13/00

CPC分类号： G06F13/4027

摘要： Control logic of a node controller receives an input vector and produces an output vector. The control logic includes a plurality of tied control store entries including hard-coded logic to identify unique values of the input vector and to produce the output vector from a hard-coded output vector when the input vector is identified and when the tied control store is enabled. The control logic also includes a plurality of spare control store entries including programmable logic configurable to identify values of the input vector and to produce the output vector from a programmable output vector when the input vector is identified and when the spare control store is enabled. One of the spare control store entries that is configured to identify a value of the input vector that none of the tied control store entries that are enabled by the entry-enables register arc configured to identify is enabled.

摘要翻译： 节点控制器的控制逻辑接收输入向量并产生输出向量。 控制逻辑包括多个连接的控制存储条目，包括用于识别输入向量的唯一值的硬编码逻辑，并且当识别输入向量时以及当绑定的控制存储器是 启用 控制逻辑还包括多个备用控制存储条目，包括可配置为识别输入向量的值的可编程逻辑，并且当识别输入向量时和当备用控制存储器被使能时，从可编程输出向量产生输出向量。 配置为标识输入向量的值之一的备用控制存储条目之一是启用了由条目启用寄存器被启用的绑定控制存储条目的所有条目。