公开(公告)号：US20230120994A1

公开(公告)日：2023-04-20

申请号：US17911693

申请日：2020-04-03

Applicant: Mitsubishi Electric Corporation

Inventor： Shuichi HIZA ,  Kunihiko NISHIMURA ,  Yuki TAKIGUCHI ,  Eiji YAGYU

IPC: H01L21/304 ,  H01L21/02

Abstract: The present disclosure relates to a semiconductor substrate manufacturing method including: forming a catalytic metal film composed of a transition metal on a main surface to be polished of a workpiece substrate composed of any one of diamond, silicon carbide, gallium nitride, and sapphire; and providing relative movement between the workpiece substrate on which the catalytic metal film has been formed and a polishing platen in an oxidant solution to remove a compound generated by chemical reaction of an active radical generated by reaction of the catalytic metal film and the oxidant solution and a surface atom on the main surface of the workpiece substrate to thereby polish the workpiece substrate. The manufacturing method further includes: bonding the polished workpiece substrate to a nitride semiconductor layer by room temperature bonding; and removing a support substrate and a resin adhesive layer.

公开(公告)号：US20220416031A1

公开(公告)日：2022-12-29

申请号：US17780521

申请日：2020-01-10

Applicant: Mitsubishi Electric Corporation

Inventor： Koji YOSHITSUGU ,  Eiji YAGYU

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/778 ,  H01L29/66

Abstract: A semiconductor device includes a nitride semiconductor laminated structure formed on a substrate, a source electrode formed on the nitride semiconductor laminated structure, a drain electrode and a gate electrode, and a surface protection film covering the nitride semiconductor laminated structure. the nitride semiconductor laminated structure includes: a first nitride semiconductor layer formed on the substrate; and a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a composition different from the first nitride semiconductor layer. The surface protection film includes: a first insulating film formed to have contact with the gate electrode; and a second insulating film formed adjacent to the first insulating film and having a higher carbon concentration than the first insulating film.

公开(公告)号：US20190129273A1

公开(公告)日：2019-05-02

申请号：US16092357

申请日：2017-02-23

Applicant: Mitsubishi Electric Corporation

Inventor： Toshiyuki TANAKA ,  Koichi AKIYAMA ,  Eiji YAGYU ,  Kiyotomo HASEGAWA

IPC: G02F1/225 ,  G02F1/017

CPC classification number: G02F1/2255 ,  G02F1/01708 ,  G02F1/025 ,  G02F1/2257 ,  G02F2001/212 ,  G02F2203/50

Abstract: The present invention has an object to provide an optical modulator having a small-sized circuit configuration and a smaller voltage drop amount in a terminating resistor. An optical modulator includes first and second optical waveguides, a first signal electrode that inputs a first high frequency signal into the first optical waveguide, a second signal electrode that inputs a second high frequency signal having a reverse phase with respect to a phase of the first high frequency signal into the second optical waveguide, a first terminating resistor connected to the first signal electrode at a terminating part side, a second terminating resistor connected to the second signal electrode at a terminating part side, a connection point that connects the first and second signal electrodes via the first and second terminating resistors, and a direct current voltage supply connected to the connection point. A resistance value of the first terminating resistor is equal to characteristic impedance of the first signal electrode. A resistance value of the second terminating resistor is equal to characteristic impedance of the second signal electrode.

公开(公告)号：US20230178590A1

公开(公告)日：2023-06-08

申请号：US17925828

申请日：2020-07-08

Applicant: Mitsubishi Electric Corporation

Inventor： Hiroaki HAYASHI ,  Eiji YAGYU

IPC: H01L29/06 ,  H01L29/872 ,  H01L29/868 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/0619 ,  H01L29/45 ,  H01L29/868 ,  H01L29/872 ,  H01L29/66083

Abstract: An object is to provide a technique that ensures to reduce a parasitic resistance of a semiconductor device while enhancing a breakdown voltage property of a semiconductor device. A portion of a second semiconductor layer exposed from a first semiconductor layer corresponds to a concave portion of a laminated structure and the first semiconductor layer or an adjacent portion of the first semiconductor layer and a second semiconductor layer corresponds to a convex portion of the laminated structure. A first guard ring of a second conductivity type is arranged on side walls of the convex portion, and in the concave portion, a guard ring of the second conductivity type is not arranged, or a second guard ring of the second conductivity type having a thickness thinner than that of the first guard ring is arranged.

公开(公告)号：US20210043539A1

公开(公告)日：2021-02-11

申请号：US16978191

申请日：2018-06-28

Applicant: Mitsubishi Electric Corporation

Inventor： Koji YOSHITSUGU ,  Keisuke NAKAMURA ,  Eiji YAGYU

IPC: H01L23/373 ,  H01L29/20 ,  H01L29/778 ,  H01L29/66 ,  H01L21/02 ,  H01L21/48 ,  H01L21/78

Abstract: A technique disclosed in this description relates to a semiconductor device and a method of manufacturing the semiconductor device, and is intended to provide a semiconductor device having high heat dissipation performance. The semiconductor device relating to the technique disclosed in this description includes a diamond substrate and a nitride semiconductor layer. The diamond substrate is made of diamond. The nitride semiconductor layer is formed in a recess formed at an upper surface of the diamond substrate.

公开(公告)号：US20170092783A1

公开(公告)日：2017-03-30

申请号：US15173740

申请日：2016-06-06

Applicant: Mitsubishi Electric Corporation

Inventor： Kenichiro KURAHASHI ,  Takuma NANJO ,  Muneyoshi SUITA ,  Akifumi IMAI ,  Eiji YAGYU ,  Hiroyuki OKAZAKI

IPC: H01L29/812 ,  H01L29/06 ,  H01L29/66 ,  H01L29/40 ,  H01L29/80

CPC classification number: H01L29/812 ,  H01L23/291 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/408 ,  H01L29/42376 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/802

Abstract: A semiconductor device includes: a substrate; a nitride semiconductor layer on the substrate; a source electrode, a drain electrode and a gate electrode on the nitride semiconductor layer; and a SiN surface protective film covering the nitride semiconductor layer, wherein a composition ratio Si/N of Si and N that form a Si—N bond of the SiN surface protective film is 0.751 to 0.801

公开(公告)号：US20230083507A1

公开(公告)日：2023-03-16

申请号：US17799272

申请日：2020-03-23

Applicant: Mitsubishi Electric Corporation

Inventor： Yuki TAKIGUCHI ,  Shuichi HIZA ,  Eiji YAGYU

IPC: H01L23/373 ,  H01L29/20 ,  H01L29/778 ,  H01L21/48 ,  H01L21/02 ,  H01L21/78

Abstract: A nitride semiconductor device includes: a diamond substrate; a first graphene layer provided on the diamond substrate; a second graphene layer provided on the first graphene layer; a nitride semiconductor layer provided on the second graphene layer; and a nitride semiconductor element having an electrode provided on the nitride semiconductor layer, wherein the first and second graphene layers are provided as an interface layer between the diamond substrate and the nitride semiconductor layer.

公开(公告)号：US20220230920A1

公开(公告)日：2022-07-21

申请号：US17605002

申请日：2019-05-23

Applicant: Mitsubishi Electric Corporation

Inventor： Shuichi HIZA ,  Kunihiko NISHIMURA ,  Masahiro FUJIKAWA ,  Yuki TAKIGUCHI ,  Eiji YAGYU

IPC: H01L21/78 ,  H01L21/02 ,  H01L21/48 ,  H01L29/20 ,  H01L23/373 ,  C30B25/18 ,  C30B33/00 ,  C30B29/40

Abstract: The present invention relates to a method for manufacturing a semiconductor substrate, including: (a) preparing an epitaxial substrate having a nitride semiconductor layer formed on a first main surface of a growth substrate and preparing a first support substrate, forming a resin adhesive layer between the first main surface of the growth substrate and a first main surface of the first support substrate, and bonding the epitaxial substrate to the first support substrate; (b) thinning a second main surface of the growth substrate; (c) forming a first protective thin film layer on the thinned growth substrate; (d) forming a second protective thin film layer on the first support substrate; (e) removing the thinned growth substrate; (0 bonding a second support substrate onto the nitride semiconductor layer; and (g) removing the first support substrate and the resin adhesive layer.

公开(公告)号：US20220059386A1

公开(公告)日：2022-02-24

申请号：US17298961

申请日：2019-02-25

Applicant: Mitsubishi Electric Corporation

Inventor： Masahiro FUJIKAWA ,  Kunihiko NISHIMURA ,  Shuichi HIZA ,  Eiji YAGYU

IPC: H01L21/683 ,  H01L21/304 ,  H01L21/67

Abstract: An object is to provide a technique capable of suppressing defectives in semiconductor elements. A manufacturing method of a semiconductor device includes a step of forming a laminated body in which an adhesive protective layer, an adhesive layer, a peeling layer, and a support substrate are disposed in this order on a first main surface of the semiconductor substrate, a step of removing the semiconductor substrate other than a portion where a plurality of circuit elements are formed, a step of bonding the portion where the circuit elements are formed to a transfer substrate, a step of removing the peeling layer, the support substrate and the adhesive layer, a step of removing the adhesive protective layer by chemical treatment, and a step of dividing the plurality of circuit elements.

公开(公告)号：US20230352599A1

公开(公告)日：2023-11-02

申请号：US17913846

申请日：2020-05-13

Applicant: Mitsubishi Electric Corporation

Inventor： Hisashi SAITO ,  Yuki TAKIGUCHI ,  Shigeyoshi USAMI ,  Takahiro YAMADA ,  Marika NAKAMURA ,  Eiji YAGYU

IPC: H01L29/808 ,  H01L29/778 ,  H01L29/205 ,  H01L29/10 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/808 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66893 ,  H01L29/7786

Abstract: A source layer is provided on a first p-type layer made of a nitride-based semiconductor, and includes a semiconductor region including electrons as carriers. A drain layer faces the source layer in a first direction on the first p-type layer with a gap being provided therebetween, and includes a semiconductor region including electrons as carriers. A channel structure is provided between the source layer and the drain layer on the first p-type layer, in which a channel region and a gate region are alternately disposed in a second direction perpendicular to the first direction. A channel layer included in the channel structure forms at least a part of the channel region, and is made of a nitride-based semiconductor. A gate layer included in the channel structure forms at least a part of the gate region, and electrically connects a gate electrode and the first p-type layer.