公开(公告)号：US11799022B2

公开(公告)日：2023-10-24

申请号：US17242587

申请日：2021-04-28

申请人： Mitsubishi Electric Corporation

发明人： Kakeru Otsuka ,  Hayato Okamoto ,  Katsumi Nakamura ,  Koji Tanaka ,  Koichi Nishi

IPC分类号： H01L29/739 ,  H01L29/66 ,  H01L27/06

CPC分类号： H01L29/7397 ,  H01L27/0635 ,  H01L29/66348

摘要： A semiconductor device includes: a drift layer of a first conduction type provided in a semiconductor substrate having a first principal plane and a second principal plane opposed to the first principal plane; a first semiconductor layer of a second conduction type provided between the first principal plane of the semiconductor substrate and the drift layer and having impurity concentration higher than impurity concentration of the drift layer; a first buffer layer of a first conduction type provided between the second principal plane of the semiconductor substrate and the drift layer and having hydrogen-induced donors with impurity concentration higher than impurity concentration of the drift layer; and a second semiconductor layer of a first conduction type or a second conduction type provided between the second principal plane of the semiconductor substrate and the first buffer layer and having impurity concentration higher than impurity concentration of the drift layer, wherein the first buffer layer includes a complex defect of interstice carbon and interstice oxygen having density decreasing from the second principal plane side toward the first principal plane side.

公开(公告)号：US11101133B2

公开(公告)日：2021-08-24

申请号：US16448225

申请日：2019-06-21

申请人： Mitsubishi Electric Corporation

发明人： Katsumi Nakamura

IPC分类号： H01L21/22 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/739 ,  H01L29/868 ,  H01L21/324 ,  H01L29/66 ,  H01L21/322 ,  H01L21/304 ,  H01L21/306 ,  H01L21/265 ,  H01L29/87

摘要： An object of the present invention is to provide stable withstand voltage characteristics, reduce turn-off losses along with a reduction in leakage current when the device is off, improve controllability of turn-off operations, and improve blocking capability at turn-off. An N buffer layer includes a first buffer layer joined to an active layer and having one peak in impurity concentration, and a second buffer layer joined to the first buffer layer and an N− drift layer, having at least one peak point in impurity concentration, and having a lower maximum impurity concentration than the first buffer layer. The impurity concentration at the peak point of the first buffer layer is higher than the impurity concentration of the N− drift layer, and the impurity concentration of the second buffer layer is higher than the impurity concentration of the N− drift layer in the entire area of the second buffer layer.

公开(公告)号：US10950461B2

公开(公告)日：2021-03-16

申请号：US16586584

申请日：2019-09-27

申请人： Mitsubishi Electric Corporation

发明人： Katsumi Nakamura

IPC分类号： H01L21/322 ,  H01L29/66 ,  H01L29/32 ,  H01L29/739 ,  H01L29/40 ,  H01L29/861 ,  H01L29/06 ,  H01L21/324 ,  H01L29/08

摘要： A semiconductor device of the present invention includes a substrate having a drift layer, metal wiring formed on an upper surface of the substrate, and an electrode formed on a back surface of the substrate, wherein the lifetime of carriers in the drift layer satisfies the following expression 1:
[Expression 1] τ≥1.5×10−5 exp(5.4×103tN−)  expression 1 τ: the lifetime of carriers in the drift layer tN−: the layer thickness of the drift layer.

公开(公告)号：US10176994B2

公开(公告)日：2019-01-08

申请号：US15545732

申请日：2015-03-13

申请人： Mitsubishi Electric Corporation

发明人： Kenji Suzuki ,  Atsushi Narazaki ,  Ryu Kamibaba ,  Yusuke Fukada ,  Katsumi Nakamura

IPC分类号： H01L29/74 ,  H01L31/111 ,  H01L21/265 ,  H01L29/739 ,  H01L29/78 ,  H01L29/861 ,  H01L21/268 ,  H01L21/283 ,  H01L21/324 ,  H01L29/08 ,  H01L29/10 ,  H01L29/167 ,  H01L29/36 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L29/45 ,  H01L29/16 ,  H01L29/20

摘要： A p-type base layer (2) is formed on a surface of an n-type silicon substrate (1). First and second n+-type buffer layers (8,9) 9 are formed on a back surface of the n-type silicon substrate (1). The first n+-type buffer layer (8) is formed by a plurality of implantations of protons at different accelerating voltages and has a plurality of peak concentrations with different depths from the back surface of the n-type silicon substrate (1). The second n+-type buffer layer (9) is formed by an implantation of a phosphorus. A position of a peak concentration of the phosphorus is shallower from the back surface of the n-type silicon substrate (1) than positions of peak concentrations of the protons. The peak concentration of the phosphorus is higher than the peak concentrations of the protons. A concentration of the protons is higher than a concentration of the phosphorus at the positions of the peak concentrations of the protons.

公开(公告)号：US10026803B1

公开(公告)日：2018-07-17

申请号：US15666096

申请日：2017-08-01

申请人： Mitsubishi Electric Corporation

发明人： Katsumi Nakamura

IPC分类号： H01L29/739 ,  H01L29/868 ,  H01L29/06 ,  H01L29/10 ,  H01L29/36 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66 ,  H02M7/537

摘要： The present invention has an object of, in a semiconductor device having a vertical structure, providing stable withstand voltage characteristics, reducing a turn-off loss with reduction in leakage current at a time of turn-off, and improving a controllability of a turn-off operation and a blocking capability at a time of turn-off.A buffer layer includes a first buffer layer being joined to an active layer and having one peak point of an impurity concentration and a second buffer layer being joined to the first buffer layer and a drift layer, having at least one peak point of an impurity concentration, and having a maximum impurity concentration lower than that of the first buffer layer, and the maximum impurity concentration of the second buffer layer is higher than the impurity concentration of the drift layer and equal to or lower than 1.0×1015 cm−3.

公开(公告)号：US09786796B2

公开(公告)日：2017-10-10

申请号：US14688640

申请日：2015-04-16

申请人： MITSUBISHI ELECTRIC CORPORATION

发明人： Katsumi Nakamura

IPC分类号： H01L29/02 ,  H01L29/861 ,  H01L29/08 ,  H01L29/739 ,  H01L29/36

CPC分类号： H01L29/861 ,  H01L29/0834 ,  H01L29/36 ,  H01L29/7397 ,  H01L29/8618

摘要： A semiconductor device having first through third layers. The first layer has a conductivity type that is different from a conductivity type of the second layer. A peak value of an impurity concentration of a portion of the third layer is greater than a peak value of an impurity concentration of the second layer. The semiconductor device allows a decrease in the forward voltage drop and also allows an improvement of the safe operating area tolerance. Thus, it is possible to decrease the forward voltage drop, improve the maximum reverse voltage, and suppress oscillations at the time of recovery.

公开(公告)号：US20140327072A1

公开(公告)日：2014-11-06

申请号：US14336800

申请日：2014-07-21

申请人： Mitsubishi Electric Corporation

发明人： Akito Nishii ,  Katsumi Nakamura

IPC分类号： H01L29/861

CPC分类号： H01L29/861 ,  H01L29/0615 ,  H01L29/0696 ,  H01L29/083 ,  H01L29/423 ,  H01L29/66348 ,  H01L29/7397

摘要： A semiconductor device includes: an N-type drift layer; a P-type anode layer on the N-type drift layer; a trench penetrating the P-type anode layer; a conductive substance embedded in the trench via an insulating film; and an N-type buffer layer between the N-type drift layer and the P-type anode layer and having impurity concentration which is higher than that of the N-type drift layer.

摘要翻译： 一种半导体器件包括：N型漂移层; N型漂移层上的P型阳极层; 穿透P型阳极层的沟槽; 通过绝缘膜嵌入沟槽中的导电物质; 以及在N型漂移层和P型阳极层之间的N型缓冲层，其杂质浓度高于N型漂移层的杂质浓度。

公开(公告)号：US11949007B2

公开(公告)日：2024-04-02

申请号：US17405451

申请日：2021-08-18

申请人： Mitsubishi Electric Corporation

发明人： Katsumi Nakamura

IPC分类号： H01L29/739 ,  H01L29/06 ,  H01L29/66 ,  H01L29/868

CPC分类号： H01L29/7397 ,  H01L29/0696 ,  H01L29/66333 ,  H01L29/868

摘要： A semiconductor device includes: an N− drift layer of a first conductivity type formed in the semiconductor substrate; a P base layer formed on the N− drift layer; and an N buffer layer of the first conductivity type formed under the N− drift layer and higher in peak impurity concentration than the N− drift layer. The N buffer layer includes: a first buffer layer in which a trap level derived from lattice defect is not detected by a photoluminescence method; and a second buffer layer provided between the first buffer layer and the N− drift layer and in which two types of trap levels derived from lattice defect are detected by the photoluminescence method.

公开(公告)号：US11444157B2

公开(公告)日：2022-09-13

申请号：US17069990

申请日：2020-10-14

申请人： Mitsubishi Electric Corporation

发明人： Kenji Suzuki ,  Koichi Nishi ,  Katsumi Nakamura

IPC分类号： H01L29/08 ,  H01L29/739 ,  H01L29/66 ,  H01L21/265 ,  H01L21/324 ,  H01L29/10

摘要： An object is to provide a technique of improving productivity of a semiconductor device. A first buffer layer includes a first portion located in a thickness direction of a semiconductor substrate from a main surface and having a first peak of an N type impurity concentration and a second portion located farther away from the main surface than the first portion and having a second peak of an N type impurity concentration. A distance from the main surface to the first portion is equal to or smaller than 4.0 μm, and a distance from the first portion to the second portion is equal to or larger than 14.5 μm. An N type impurity concentration of a portion between the first portion and the second portion is higher than an N type impurity concentration of a drift layer.

公开(公告)号：US10411093B2

公开(公告)日：2019-09-10

申请号：US15755098

申请日：2015-12-28

申请人： Mitsubishi Electric Corporation

发明人： Katsumi Nakamura ,  Tatsuo Harada ,  Noritsugu Nomura

IPC分类号： H01L29/08 ,  H01L29/78 ,  H01L29/861 ,  H01L29/868 ,  H01L21/04 ,  H01L21/225 ,  H01L29/06 ,  H01L29/739 ,  H01L29/36 ,  H01L29/66 ,  H01L29/16 ,  H01L29/20 ,  H01L21/263

摘要： An active cell region, an edge termination region surrounding the active cell region and an intermediate region located at an intermediate position between these regions are provided, the active cell region has a trench gate type MOS structure on a top side, and a vertical structure on a bottom side includes a p-collector layer, an n-buffer layer on the p-collector layer, and an n-drift layer on the n-buffer layer, the n-buffer layer has a first buffer portion provided on the p-collector layer side, and a second buffer portion provided on the n-drift layer side, the peak impurity concentration of the first buffer portion is higher than the peak impurity concentration of the second buffer portion, and the impurity concentration gradient on the n-drift layer side of the second buffer portion is gentler than the impurity concentration gradient on the n-drift layer side of the first buffer portion.