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公开(公告)号：US20230017177A1
公开(公告)日：2023-01-19
申请号：US17948993
申请日：2022-09-20
发明人： Sho IKEDA , Koji TSUTSUMI , Masaomi TSURU
IPC分类号： H03L7/081
摘要： A delay synchronization circuit includes a pulse synthesizing circuit to generate a synthesized signal including a first pulse signal synchronized with a reference signal and a second pulse signal synchronized a feedback signal, a VCDL to delay the synthesized signal g and output a delayed synthesized signal, a pulse separation circuit to generate a first separation signal synchronized with a first pulse signal included in the delayed synthesized signal and generate a second separation signal synchronized with a second pulse signal included in the delayed synthesized signal, a circulator to output a first separation signal to a clock reception circuit and then output the first separation signal returned from the clock reception circuit to the pulse synthesizing circuit as the feedback signal, and a delay-amount control circuit to control a delay amount of the delayed synthesized signal according to a phase difference between the reference signal and the second separation signal.
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公开(公告)号：US20210083681A1
公开(公告)日：2021-03-18
申请号：US17107382
申请日：2020-11-30
发明人： Sho IKEDA , Akihito HIRAI , Koji TSUTSUMI , Mitsuhiro SHIMOZAWA
摘要： A phase-locked loop circuit includes: a division ratio control circuit controlling a division ratio of an output signal of a variable frequency divider on the basis of an addition signal of a negative feedback signal and a division ratio setting signal indicating the division ratio, in synchronization with a divided signal output from the variable frequency divider; a first phase detection circuit calculating a first phase detection signal indicating a phase of an output signal of a signal output circuit; a second phase detection circuit calculating a second phase detection signal indicating a phase of the output signal of a case where it is assumed that the division ratio control circuit controls the division ratio of the output signal of the variable frequency divider in synchronization with the reference signal; and a shift circuit generating a negative feedback signal from a difference between the first phase detection signal and the second phase detection signal, and outputting an addition signal of the generated negative feedback signal and the division ratio setting signal to the division ratio control circuit.
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公开(公告)号：US20220349992A1
公开(公告)日：2022-11-03
申请号：US17866809
申请日：2022-07-18
发明人： Koji TSUTSUMI , Sho IKEDA
摘要： In a radar device, a reception antenna directly receives a chirp signal transmitted by a transmission antenna of a module other than a module to which the reception antenna belongs among a plurality of modules, a mixer generates a baseband signal by mixing a chirp signal generated by a chirp signal source and a chirp signal received by the reception antenna, and an analog-to-digital converter generates a digital signal by digital-converting the baseband signal generated by the mixer.
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公开(公告)号：US20220224507A1
公开(公告)日：2022-07-14
申请号：US17710377
申请日：2022-03-31
发明人： Hiroyuki MIZUTANI , Sho IKEDA , Kae MORITA
摘要： In a case where signals branched from a single reference signal source are transmitted via a plurality of cables, a phase synchronization circuit can be used to stabilize a phase of a signal to be outputted from each cable. However, the phases of signal to be outputted from each cable is affected by combination of a length of each cable and an amount of delay caused by feedback control, so that phases of synchronization signals to be outputted from a plurality of transmission paths are not always the same as each other. In the present invention, since a frequency multiplier that multiplies a frequency of a signal outputted from each transmission path by an even number is provided for a phase synchronization circuit, the phases of the synchronization signals to be outputted from the transmission paths are aligned even when signals are branched from one reference signal.
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公开(公告)号：US20210376817A1
公开(公告)日：2021-12-02
申请号：US17405109
申请日：2021-08-18
发明人： Wataru YAMAMOTO , Koji TSUTSUMI , Sho IKEDA , Masaomi TSURU
摘要： A phase-variable frequency multiplier includes: a 90-degree divider for dividing an input signal into an I-signal and a Q-signal; an amplitude setting circuit for distributing each of the I-signal and the Q-signal to two paths, setting amplitudes of two of four signals including the two distributed I-signals and the two distributed Q-signals depending on a phase shift amount of the input signal, and outputting as set signals, the four signals including the signals with the set amplitudes; a first mixer for multiplying one of the two I-signals included in the set signals by one of the two Q-signals included in the set signals to generate a first signal having a frequency being twice the frequency of the input signal; a second mixer for multiplying the other of the two I-signals included in the set signals by the other of the two Q-signals included in the set signals to generate a second signal with an amplitude ratio with respect to the first signal, being a tangent or a reciprocal of a tangent of the phase shift amount and with a frequency being twice the frequency of the input signal; and a 90-degree combiner for applying a phase difference of 90 degrees between the first signal and the second signal, and combining the first signal having the phase difference of 90 degrees from the second signal with the second signal.
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公开(公告)号：US20210211134A1
公开(公告)日：2021-07-08
申请号：US17210923
申请日：2021-03-24
发明人： Koji TSUTSUMI , Sho IKEDA
摘要： A lock detection circuit is configured to include an integrating circuit that integrates a phase difference between a frequency-divided signal of a VCO and a reference signal during a constant period within a transient response period for an output signal from the VCO, and integrates a phase difference between the frequency-divided signal and the reference signal during a constant period within a convergence period for the output signal from the VCO; and a degree-of-convergence calculating circuit that calculates a degree at which the output signal from the VCO has converged, from a result of the integration of the phase difference obtained by the integrating circuit during the constant period within the transient response period and a result of the integration of the phase difference obtained by the integrating circuit during the constant period within the convergence period.
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