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公开(公告)号：US08497638B2
公开(公告)日：2013-07-30
申请号：US12868776
申请日：2010-08-26
IPC分类号： H05B37/02
CPC分类号： G02F1/133603 , G02F2001/133612 , G09G3/3406 , G09G2300/0426 , G09G2320/02 , G09G2320/064
摘要： A light source device which is used as the backlight device and does not generate sound is provided. One or more flat substrates each having a light emitting element on its surface side are supported by a chassis having a conductive flat plate surface so that back surfaces of the substrates are opposed to the flat plate surface. The substrate comprises first wiring conductive thin films on a surface side of an insulation substrate, and one or more second radiating or wiring conductive thin films on a back surface side of the insulation substrate. Two terminals of the light emitting element are connected to the two adjacent first conductive thin films. A potential of at least one of the second conductive thin films is fixed to have a constant potential difference or preferably fixed to the same potential with respect to that of the flat plate surface of the chassis.
摘要翻译： 提供用作背光装置并且不产生声音的光源装置。 在其表面侧具有发光元件的一个或多个平面基板由具有导电平板表面的底架支撑，使得基板的背面与平板表面相对。 基板包括在绝缘基板的表面侧上的第一布线导电薄膜和在绝缘基板的背面侧上的一个或多个第二辐射或布线导电薄膜。 发光元件的两个端子连接到两个相邻的第一导电薄膜。 第二导电薄膜中的至少一个的电位被固定为具有恒定的电位差，或者优选地相对于底盘的平板表面固定在相同的电位上。
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2.发明授权High-level synthesis apparatus, high-level synthesis method, method for producing logic circuit using the high-level synthesis method, and recording medium 失效高级合成装置，高级合成方法，使用高级合成方法生成逻辑电路的方法和记录介质公开(公告)号：US06832363B2
公开(公告)日：2004-12-14
申请号：US10166094
申请日：2002-06-11
申请人： Mitsuhisa Ohnishi
发明人： Mitsuhisa Ohnishi
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： A high-level synthesis apparatus for synthesizing a register transfer level logic circuit from a behavioral description describing a processing operation of the circuit, comprises a low power consumption circuit generation section for generating a low power consumption circuit which stops or inhibits circuit operations of partial circuits constituting the logic circuit only when the partial circuits are in a wait state, so to achieve low power consumption. The low power consumption circuit generation section is synthesized along with the logic circuit.
摘要翻译： 一种用于从描述电路的处理操作的行为描述合成寄存器传送电平逻辑电路的高级合成装置包括：低功耗电路产生部分，用于产生停止或禁止部分电路的电路操作的低功耗电路 仅当部分电路处于等待状态时才构成逻辑电路，从而实现低功耗。 低功耗电路生成部与逻辑电路一起合成。
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公开(公告)号：US08908982B2
公开(公告)日：2014-12-09
申请号：US13989963
申请日：2011-09-26
IPC分类号： G06K9/36 , G06K9/46 , G06T9/00 , H04N19/90 , H04N19/50 , H04N19/149 , H04N19/103 , H04N19/182 , H04N1/64
CPC分类号： G06T9/00 , H04N1/64 , H04N19/103 , H04N19/146 , H04N19/15 , H04N19/169 , H04N19/182 , H04N19/50
摘要： The present invention provides an image encoding device that can balance encoding at a high compression ratio and restoration of a high-quality image by decoding in a short processing time. Compression mode determination means 3 determines a compression mode to be one of DPCM and PCM based on target pixel data inputted from a terminal 21 and predicted data calculated by a predetermined method. For the DPCM, DPCM compression means 5 compresses a difference value between the target pixel data and the predicted data to DPCM encoded data having a predetermined DPCM code length. For the PCM, PCM compression means 7 compresses the target pixel data to PCM encoded data having a PCM code length determined by PCM code length determination means 9. The PCM code length determination means 9 calculates the PCM code length for each piece of target pixel data such that a total of post-encoding code lengths becomes an allowable value or less in a unit of predetermined pixel group among the plurality of pixels. Tag/code output means 13 outputs the encoded data by adding a tag indicating whether the compression mode is the DPCM or the PCM to the encoded data.
摘要翻译： 本发明提供一种图像编码装置，其可以在短的处理时间内通过解码来平衡高压缩比的编码和高品质图像的恢复。 压缩模式确定装置3基于从终端21输入的目标像素数据和通过预定方法计算出的预测数据，确定压缩模式为DPCM和PCM之一。 对于DPCM，DPCM压缩装置5将目标像素数据和预测数据之间的差值压缩到具有预定DPCM码长度的DPCM编码数据。 对于PCM，PCM压缩装置7将目标像素数据压缩为具有由PCM码长度确定装置9确定的PCM码长度的PCM编码数据。PCM码长度确定装置9计算每个目标像素数据的PCM码长度 使得总共的后编码码长度成为多个像素中的预定像素组的单位的容许值以下。 标签/代码输出装置13通过将指示压缩模式是DPCM或PCM的标签添加到编码数据来输出编码数据。
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4.发明授权High level synthesis device, method for generating a model for verifying hardware, method for verifying hardware, control program, and readable recording medium 有权高级合成装置，用于生成用于验证硬件的模型的方法，用于验证硬件的方法，控制程序和可读记录介质公开(公告)号：US07266791B2
公开(公告)日：2007-09-04
申请号：US10850153
申请日：2004-05-21
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A high level synthesis device includes a high level synthesis section and a cycle accurate model. The high level synthesis section may perform high level synthesis of hardware including a plurality of components and a controller for controlling the plurality of components. The cycle accurate model may be configured to verify a state of at least one of the plurality of components and the controller at a cycle accurate level, with a general-purpose programming language.
摘要翻译： 高级合成装置包括高级合成部分和循环精确模型。 高级合成部分可以执行包括多个部件的硬件的高级合成以及用于控制多个部件的控制器。 循环精确模型可以被配置为利用通用编程语言来以循环准确水平来验证多个组件和控制器中的至少一个的状态。
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5.发明申请High level synthesis device, method for generating a model for verifying hardware, method for verifying hardware, control program, and readable recording medium 有权高级合成装置，用于生成用于验证硬件的模型的方法，用于验证硬件的方法，控制程序和可读记录介质公开(公告)号：US20050010387A1
公开(公告)日：2005-01-13
申请号：US10850153
申请日：2004-05-21
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A high level synthesis device includes a high level synthesis section for performing high level synthesis of hardware including a plurality of components and a controller for controlling the plurality of components; and a cycle accurate model generation section for generating a cycle accurate model, capable of verifying a state of at least one of the plurality of components and the controller at a cycle accurate level, with a general-purpose programming language.
摘要翻译： 高级合成装置包括用于执行包括多个部件的硬件的高级合成的高级合成部分和用于控制多个部件的控制器; 以及循环精确模型生成部，用于生成周期精确模型，能够以通用编程语言以循环准确度来验证多个部件中的至少一个和控制器的状态。
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公开(公告)号：US20130251257A1
公开(公告)日：2013-09-26
申请号：US13989963
申请日：2011-09-26
IPC分类号： G06T9/00
CPC分类号： G06T9/00 , H04N1/64 , H04N19/103 , H04N19/146 , H04N19/15 , H04N19/169 , H04N19/182 , H04N19/50
摘要： The present invention provides an image encoding device that can balance encoding at a high compression ratio and restoration of a high-quality image by decoding in a short processing time. Compression mode determination means 3 determines a compression mode to be one of DPCM and PCM based on target pixel data inputted from a terminal 21 and predicted data calculated by a predetermined method. For the DPCM, DPCM compression means 5 compresses a difference value between the target pixel data and the predicted data to DPCM encoded data having a predetermined DPCM code length. For the PCM, PCM compression means 7 compresses the target pixel data to PCM encoded data having a PCM code length determined by PCM code length determination means 9. The PCM code length determination means 9 calculates the PCM code length for each piece of target pixel data such that a total of post-encoding code lengths becomes an allowable value or less in a unit of predetermined pixel group among the plurality of pixels. Tag/code output means 13 outputs the encoded data by adding a tag indicating whether the compression mode is the DPCM or the PCM to the encoded data.
摘要翻译： 本发明提供一种图像编码装置，其可以在短的处理时间内通过解码来平衡高压缩比的编码和高品质图像的恢复。 压缩模式确定装置3基于从终端21输入的目标像素数据和通过预定方法计算出的预测数据，确定压缩模式为DPCM和PCM之一。 对于DPCM，DPCM压缩装置5将目标像素数据和预测数据之间的差值压缩到具有预定DPCM码长度的DPCM编码数据。 对于PCM，PCM压缩装置7将目标像素数据压缩为具有由PCM码长度确定装置9确定的PCM码长度的PCM编码数据。PCM码长度确定装置9计算每个目标像素数据的PCM码长度 使得总共的后编码码长度成为多个像素中的预定像素组的单位的容许值以下。 标签/代码输出装置13通过将指示压缩模式是DPCM或PCM的标签添加到编码数据来输出编码数据。
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公开(公告)号：US20110050111A1
公开(公告)日：2011-03-03
申请号：US12868776
申请日：2010-08-26
IPC分类号： H05B37/02
CPC分类号： G02F1/133603 , G02F2001/133612 , G09G3/3406 , G09G2300/0426 , G09G2320/02 , G09G2320/064
摘要： A light source device which is used as the backlight device and does not generate sound is provided. One or more flat substrates each having a light emitting element on its surface side are supported by a chassis having a conductive flat plate surface so that back surfaces of the substrates are opposed to the flat plate surface. The substrate comprises first wiring conductive thin films on a surface side of an insulation substrate, and one or more second radiating or wiring conductive thin films on a back surface side of the insulation substrate. Two terminals of the light emitting element are connected to the two adjacent first conductive thin films. A potential of at least one of the second conductive thin films is fixed to have a constant potential difference or preferably fixed to the same potential with respect to that of the flat plate surface of the chassis.
摘要翻译： 提供用作背光装置并且不产生声音的光源装置。 在其表面侧具有发光元件的一个或多个平面基板由具有导电平板表面的底架支撑，使得基板的背面与平板表面相对。 基板包括在绝缘基板的表面侧上的第一布线导电薄膜和在绝缘基板的背面侧上的一个或多个第二辐射或布线导电薄膜。 发光元件的两个端子连接到两个相邻的第一导电薄膜。 第二导电薄膜中的至少一个的电位被固定为具有恒定的电位差，或者优选地相对于底盘的平板表面固定在相同的电位上。
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公开(公告)号：US07178064B2
公开(公告)日：2007-02-13
申请号：US10730380
申请日：2003-12-09
申请人： Hiroichi Makida , Mitsuhisa Ohnishi
发明人： Hiroichi Makida , Mitsuhisa Ohnishi
IPC分类号： G06F11/00
CPC分类号： G06F11/362
摘要： A debug device has a serialization section for converting a parallel program to a serial program and creating debug data indicating the corresponding relation between the parallel program and the serial program. The debug device further has a storage section for storing the debug data and a conversion section for mutually converting the corresponding data between the parallel program and the serial program based on the debug data in order for an operator to efficiently perform a debug operation.
摘要翻译： 调试装置具有串行化部分，用于将并行程序转换为串行程序，并创建指示并行程序和串行程序之间的对应关系的调试数据。 调试装置还具有用于存储调试数据的存储部分和用于基于调试数据在并行程序和串行程序之间相互转换相应数据的转换部分，以便操作者有效地执行调试操作。
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9.发明授权High-level synthesis method, high-level synthesis apparatus, method for producing logic circuit using the high-level synthesis method for logic circuit design, and recording medium 失效高级合成方法，高级合成装置，使用逻辑电路设计的高级合成方法生成逻辑电路的方法和记录介质公开(公告)号：US06687894B2
公开(公告)日：2004-02-03
申请号：US09984897
申请日：2001-10-31
申请人： Mitsuhisa Ohnishi , Shinichi Tanaka
发明人： Mitsuhisa Ohnishi , Shinichi Tanaka
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： A high-level synthesis method is provided for synthesizing a register transfer level logic circuit based on a behavioral description in which processing behaviors are described. The method includes the steps of extracting information on a bus connection resource from the behavioral description, storing the information on the bus connection resource in a bus connection resource database, referencing the bus connection resource database, referencing a bus protocol library having a preloaded bus protocol, and automatically generating a target interface circuit based on a result of each of the bus connection resource database referencing step and the bus protocol library referencing step.
摘要翻译： 提供了一种基于描述处理行为的行为描述来合成寄存器传送电平逻辑电路的高级合成方法。 该方法包括以下步骤：从行为描述中提取关于总线连接资源的信息，将总线连接资源上的信息存储在总线连接资源数据库中，参考总线连接资源数据库，参考具有预加载总线协议的总线协议库 并且基于总线连接资源数据库参考步骤和总线协议库参考步骤中的每一个的结果自动生成目标接口电路。
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公开(公告)号：US6021381A
公开(公告)日：2000-02-01
申请号：US858763
申请日：1997-05-19
申请人： Mitsuhisa Ohnishi
发明人： Mitsuhisa Ohnishi
CPC分类号： G06F17/5022
摘要： A system for detecting power consumption of an integrated circuit obtains a frequency of data holding operations, unreferred data storing operations, and unupdated data storing operations with a data holding operation frequency calculating section, an unreferred data storing operation frequency calculating section, and an unupdated data storing operation frequency calculating section based on the number of times of a signal transition from connection information of the integrated circuit and control conditions when data is referred to registers, and obtains power consumption caused by each of the operations from the number of times of the signal transition, a load capacity, and an operation voltage. In this manner, the system distinguishes, in a function design phase, between signal transitions in the designed integrated circuit that are necessary to processing and those that are not definitely necessary, and detects reducible power consumption caused by the signal transitions that are not definitely necessary. Places where improvements can be made to reduce the power consumption of the circuit can be thus detected at an earlier phase in the design process.
摘要翻译： 用于检测集成电路的功耗的系统通过数据保持操作频率计算部分获得数据保持操作的频率，不可延迟的数据存储操作和未更新的数据存储操作，不可靠数据存储操作频率计算部分和未更新的数据 存储操作频率计算部分，基于从集成电路的连接信息进行的信号转换的次数和数据被引用到寄存器时的控制条件，并且从该信号的次数中获得由每个操作引起的功耗 转换，负载能力和工作电压。 以这种方式，系统在功能设计阶段区分处理所需的设计的集成电路中的信号转换与不是绝对必要的信号转换之间的差异，并且检测由不是绝对必要的信号转换引起的可减少功耗 。 因此可以在设计过程的较早阶段检测到可以进行改进以减少电路功耗的地方。
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