Devices and methods for pixel discharge before display turn-off
    3.
    发明授权
    Devices and methods for pixel discharge before display turn-off 有权
    显示关闭前像素放电的设备和方法

    公开(公告)号:US09111500B2

    公开(公告)日:2015-08-18

    申请号:US13451389

    申请日:2012-04-19

    IPC分类号: G06F3/038 G09G3/36

    摘要: Methods and devices employing circuitry for quickly discharging pixels of a display before the display is turned off are provided. In one example, a method may include receiving at the electronic display a signal indicating the electronic display will be powered off within a period of time. The method may also include, in response to the signal, causing a frame of pixel data originating from the electronic display to be stored in pixels of the electronic display before the electronic display is powered off. Storing the frame of pixel data in the pixels may inhibit image artifacts from occurring on the electronic display when the electronic display is powered back on in the future.

    摘要翻译: 提供了在显示器关闭之前使用用于快速放电显示器的像素的电路的方法和装置。 在一个示例中,方法可以包括在电子显示器处接收指示电子显示器将在一段时间内被断电的信号。 该方法还可以包括响应于该信号,在电子显示器断电之前,使来自电子显示器的像素数据的帧被存储在电子显示器的像素中。 将像素数据的帧存储在像素中可能会在电子显示器将来重新接通电源时抑制在电子显示器上发生的图像伪影。

    VOLTAGE THRESHOLD DETERMINATION FOR A PIXEL TRANSISTOR
    4.
    发明申请
    VOLTAGE THRESHOLD DETERMINATION FOR A PIXEL TRANSISTOR 审中-公开
    用于像素晶体管的电压阈值确定

    公开(公告)号:US20130328749A1

    公开(公告)日:2013-12-12

    申请号:US13592176

    申请日:2012-08-22

    IPC分类号: G09G3/20

    摘要: A display is disclosed that includes a transparent substrate and a plurality of pixel transistors that are formed on the transparent substrate to generate an image for display. A transistor drive circuit is used to drive the pixel transistors to generate the image. The transistor drive circuit may include a gate driver. Further, a test circuit may be used to: adjust voltages that are applied by the gate driver to a pixel transistor; and determine the voltage of the gate driver when a current spike has occurred to the pixel transistor which causes the pixel transistor to turn on. Once this threshold voltage for the gate driver to turn on the pixel transistor has been determined, it may be stored in a storage device for future use by the gate driver. Other embodiments are also described and claimed.

    摘要翻译: 公开了一种显示器,其包括透明基板和形成在透明基板上以产生用于显示的图像的多个像素晶体管。 晶体管驱动电路用于驱动像素晶体管以产生图像。 晶体管驱动电路可以包括栅极驱动器。 此外,测试电路可以用于:将由栅极驱动器施加的电压调整到像素晶体管; 并且当使像素晶体管导通的像素晶体管发生电流尖峰时,确定栅极驱动器的电压。 一旦栅极驱动器接通像素晶体管的阈值电压就被确定,它可能被存储在存储器件中以供门驱动器将来使用。 还描述和要求保护其他实施例。

    DEVICES AND METHODS FOR PIXEL DISCHARGE BEFORE DISPLAY TURN-OFF
    5.
    发明申请
    DEVICES AND METHODS FOR PIXEL DISCHARGE BEFORE DISPLAY TURN-OFF 有权
    显示器关闭之前的像素放电的设备和方法

    公开(公告)号:US20130278581A1

    公开(公告)日:2013-10-24

    申请号:US13451389

    申请日:2012-04-19

    IPC分类号: G09G3/36 G06F3/038

    摘要: Methods and devices employing circuitry for quickly discharging pixels of a display before the display is turned off are provided. In one example, a method may include receiving at the electronic display a signal indicating the electronic display will be powered off within a period of time. The method may also include, in response to the signal, causing a frame of pixel data originating from the electronic display to be stored in pixels of the electronic display before the electronic display is powered off. Storing the frame of pixel data in the pixels may inhibit image artifacts from occurring on the electronic display when the electronic display is powered back on in the future.

    摘要翻译: 提供了在显示器关闭之前使用用于快速放电显示器的像素的电路的方法和装置。 在一个示例中,方法可以包括在电子显示器处接收指示电子显示器将在一段时间内被断电的信号。 该方法还可以包括响应于该信号,在电子显示器断电之前,使来自电子显示器的像素数据的帧被存储在电子显示器的像素中。 将像素数据的帧存储在像素中可能会在电子显示器将来重新接通电源时抑制在电子显示器上发生的图像伪影。

    Systems and methods for mura calibration preparation
    7.
    发明授权
    Systems and methods for mura calibration preparation 有权
    mura校准准备的系统和方法

    公开(公告)号:US09519164B2

    公开(公告)日:2016-12-13

    申请号:US13601529

    申请日:2012-08-31

    摘要: Systems and methods for calibrating an electronic display to reduce or eliminate artifacts are provided. One method for reducing or eliminating artifacts may involve baking the operational—but not yet fully calibrated—electronic display to reduce stray charge on the electronic display. After baking the display, the electronic display may be calibrated to reduce or eliminate flicker and/or mura artifacts

    摘要翻译: 提供了用于校准电子显示器以减少或消除伪影的系统和方法。 用于减少或消除伪像的一种方法可能包括烘烤操作但尚未完全校准的电子显示器以减少电子显示器上的杂散电荷。 在烘烤显示器之后,可以校准电子显示器以减少或消除闪烁和/或凹陷伪影

    Systems and methods for dynamic dwelling time for tuning display to reduce or eliminate mura artifact
    9.
    发明授权
    Systems and methods for dynamic dwelling time for tuning display to reduce or eliminate mura artifact 有权
    用于调整显示的动态住宅时间的系统和方法,以减少或消除mura伪影

    公开(公告)号:US08988471B2

    公开(公告)日:2015-03-24

    申请号:US13601801

    申请日:2012-08-31

    IPC分类号: G09G5/10

    摘要: Systems and methods for calibrating an electronic display to reduce or eliminate a mura artifact are provided. The mura artifact may be due to differential behavior of common voltage layers (VCOMs) in the electronic display. One method for reducing or eliminating the mura artifact may involve turning on an electronic display and programming pixels the electronic display to a uniform gray level. An initial luminance value may be determined and, after waiting a period of time, a subsequent luminance of the pixels may be measured. When a difference between the subsequent luminance and initial luminance is within a threshold, the mura artifact may be understood to have settled and the electronic display may be calibrated.

    摘要翻译: 提供了用于校准电子显示器以减少或消除mura伪影的系统和方法。 该mura伪影可能是由于电子显示器中的公共电压层(VCOM)的差异行为。 用于减少或消除凹陷假象的一种方法可以包括打开电子显示器并将电子显示器的像素编程为均匀的灰度级。 可以确定初始亮度值,并且在等待一段时间之后,可以测量像素的后续亮度。 当随后的亮度和初始亮度之间的差在阈值以内时,可以理解到mura伪影已经确定并且可以校准电子显示器。

    Systems and Methods for Dynamic Dwelling Time for Tuning Display to Reduce or Eliminate Mura Artifact
    10.
    发明申请
    Systems and Methods for Dynamic Dwelling Time for Tuning Display to Reduce or Eliminate Mura Artifact 有权
    动态停留时间的系统和方法用于调整显示以减少或消除Mura人工制品

    公开(公告)号:US20130329057A1

    公开(公告)日:2013-12-12

    申请号:US13601801

    申请日:2012-08-31

    IPC分类号: H04N17/00 H01R43/00 G09G5/10

    摘要: Systems and methods for calibrating an electronic display to reduce or eliminate a mura artifact are provided. The mura artifact may be due to differential behavior of common voltage layers (VCOMs) in the electronic display. One method for reducing or eliminating the mura artifact may involve turning on an electronic display and programming pixels the electronic display to a uniform gray level. An initial luminance value may be determined and, after waiting a period of time, a subsequent luminance of the pixels may be measured. When a difference between the subsequent luminance and initial luminance is within a threshold, the mura artifact may be understood to have settled and the electronic display may be calibrated.

    摘要翻译: 提供了用于校准电子显示器以减少或消除mura伪影的系统和方法。 该mura伪影可能是由于电子显示器中的公共电压层(VCOM)的差异行为。 用于减少或消除凹陷假象的一种方法可以包括打开电子显示器并将电子显示器的像素编程为均匀的灰度级。 可以确定初始亮度值,并且在等待一段时间之后,可以测量像素的后续亮度。 当随后的亮度和初始亮度之间的差在阈值以内时,可以理解到mura伪影已经确定并且可以校准电子显示器。