公开(公告)号：US06930362B1

公开(公告)日：2005-08-16

申请号：US10698167

申请日：2003-10-30

申请人： Mohammad R. Mirabedini ,  Grace S. Sun ,  Sheldon Aronowitz

发明人： Mohammad R. Mirabedini ,  Grace S. Sun ,  Sheldon Aronowitz

IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/6656 ,  H01L21/265 ,  H01L21/28035 ,  H01L29/4925 ,  H01L29/78

摘要： A calcium doped polysilicon gate electrodes for PMOS containing semiconductor devices. The calcium doped PMOS gate electrodes reduce migration of the boron dopant out of the gate electrode, through the gate dielectric and into the substrate thereby reducing the boron penetration problem increasingly encountered with smaller device size regimes and their thinner gate dielectrics. Calcium doping of the gate electrode may be achieved by a variety of techniques. It is further believed that the calcium doping may improve the boron dopant activation in the gate electrode, thereby further improving performance.

摘要翻译： 用于含PMOS半导体器件的掺杂钙的多晶硅栅电极。 掺杂钙的PMOS栅电极减少了硼掺杂剂离开栅极电极的迁移，通过栅极电介质并进入衬底中，从而减小了越来越多的器件尺寸状态和其更薄的栅极电介质越来越多地遇到的硼渗透问题。 栅电极的钙掺杂可以通过各种技术来实现。 进一步认为钙掺杂可以改善栅电极中的硼掺杂剂活化，从而进一步提高性能。

公开(公告)号：US07132336B1

公开(公告)日：2006-11-07

申请号：US10123263

申请日：2002-04-15

申请人： Sheldon Aronowitz ,  Vladimir Zubkov ,  Grace S. Sun

发明人： Sheldon Aronowitz ,  Vladimir Zubkov ,  Grace S. Sun

IPC分类号： H01L21/336

CPC分类号： H01L29/513 ,  H01L21/265 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/31155 ,  H01L29/517 ,  H01L29/78

摘要： An improved semiconductor memory structure and methods for its fabrication are disclosed. The memory structure includes a semiconductor substrate having a dielectric region formed over a channel region. A doped region is formed between a top portion and a bottom portion of the dielectric region. This doped region includes a suitable electron affinity material. A gate electrode is connected with the top of the dielectric region. In some embodiments, suitable electron affinity materials are introduced into the doped region using implantation techniques. In another embodiment, the electron affinity material is introduced into the doped region using plasma treatment of the dielectric region and the redeposition of additional dielectric material on top of the dielectric region and doped region.

摘要翻译： 公开了一种改进的半导体存储器结构及其制造方法。 存储器结构包括具有形成在沟道区上的电介质区域的半导体衬底。 在电介质区域的顶部和底部之间形成掺杂区域。 该掺杂区域包括合适的电子亲和性材料。 栅电极与电介质区域的顶部连接。 在一些实施方案中，使用注入技术将合适的电子亲和性材料引入掺杂区域。 在另一个实施方案中，使用电介质区域的等离子体处理和在介电区域和掺杂区域的顶部上再沉积附加电介质材料将电子亲和性材料引入掺杂区域。

公开(公告)号：US06989565B1

公开(公告)日：2006-01-24

申请号：US10698169

申请日：2003-10-31

申请人： Sheldon Aronowitz ,  Vladimir Zubkov ,  Grace S. Sun

发明人： Sheldon Aronowitz ,  Vladimir Zubkov ,  Grace S. Sun

IPC分类号： H01L29/792

CPC分类号： H01L29/517 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/78

摘要： An improved semiconductor memory structure and methods for its fabrication are disclosed. The memory structure includes a semiconductor substrate having a dielectric stack formed over a channel region of a semiconductor substrate. The dielectric stack includes a layer of electron trapping material that operates as a charge storage center for memory devices. A gate electrode is connected with the top of the dielectric stack. In various embodiments the electron trapping material forms a greater or lesser portion of the dielectric stack. The invention includes a method embodiment for forming such a memory device.

摘要翻译： 公开了一种改进的半导体存储器结构及其制造方法。 存储器结构包括具有在半导体衬底的沟道区上形成的电介质叠层的半导体衬底。 电介质堆叠包括作为存储器件的电荷存储中心工作的电子俘获材料层。 栅电极与电介质叠层的顶部连接。 在各种实施例中，电子捕获材料形成介电叠层的更大或更小部分。 本发明包括用于形成这种存储器件的方法实施例。