公开(公告)号：US06788728B1

公开(公告)日：2004-09-07

申请号：US09478265

申请日：2000-01-05

申请人： Mohit K. Prasad ,  Sam Heidari

发明人： Mohit K. Prasad ,  Sam Heidari

IPC分类号： H04B1713

CPC分类号： H04J13/10 ,  H04B2201/70706 ,  H04L27/18

摘要： A reverse link modulator modulates the incoming data sequence for the I and Q channels of a wireless device such that the resulting spreading sequence never undergoes a transition through the origin. Consequently, the modulator has a reduced peak-to-average ratio and provides an improved battery life.

摘要翻译： 反向链路调制器调制无线设备的I和Q信道的输入数据序列，使得所得到的扩展序列从不经历通过原点的转换。 因此，调制器具有降低的峰均比，并提供改善的电池寿命。

公开(公告)号：US06324205B1

公开(公告)日：2001-11-27

申请号：US09566907

申请日：2000-05-09

申请人： Mohit K. Prasad

发明人： Mohit K. Prasad

IPC分类号： H04B169

CPC分类号： H04J13/10 ,  H04B1/707 ,  H04B2201/70711 ,  H04J13/0029

摘要： A scalable method and system for generating a 3X long code sequence for use in a CDMA communication system uses Gold sequences. A preferred pair of 1X long code sequences both running at 1.2288 Mchips/s are used to generate the 3X sequence. The 3X sequence so generated is a pseudo-random sequence with well defined auto-correlation and cross-correlation properties. Because the method is scalable it is easily scaled to generate other long code e.g. 6X, 9X, and 12X sequences.

摘要翻译： 用于生成用于CDMA通信系统的3X长码序列的可扩展方法和系统使用Gold序列。 使用以1.2288 Mchips / s运行的优选的1X长码序列来生成3X序列。 如此生成的3X序列是具有良好定义的自相关和互相关属性的伪随机序列。 因为该方法是可扩展的，所以容易地缩放以产生其他长码，例如 6X，9X和12X序列。

公开(公告)号：US06195344B1

公开(公告)日：2001-02-27

申请号：US09042397

申请日：1998-03-13

申请人： Mohit K. Prasad

发明人： Mohit K. Prasad

IPC分类号： H04J1300

CPC分类号： H04L1/0071 ,  H03M13/271 ,  H03M13/2764 ,  H04L1/0052

摘要： De-interleaving of forward-link paging or traffic channels is performed by implementing closed-form expressions that are equivalent to the table-based processing specified in the cdmaOne telecommunication specification. The implementation can be in either hardware or software or a combination of both. For each cdmaOne forward-link paging or traffic channel, the closed-form expression relates each interleaved symbol position to a corresponding de-interleaved symbol position, which is used to generate a de-interleaved symbol stream from the interleaved symbol stream. In one hardware implementation, the forward-link de-interleaver of the present invention has an address generation unit made from two modulo counters.

摘要翻译： 前向链路寻呼或业务信道的去交织通过实现与cdmaOne电信规范中规定的基于表的处理相同的闭合表达式来执行。 该实现可以是硬件或软件，也可以是两者的组合。 对于每个cdmaOne前向链路寻呼或业务信道，闭合形式的表达式将每个交织的符号位置与相应的去交织的符号位置相关联，该符号位置用于从交织的符号流生成去交织的符号流。 在一个硬件实现中，本发明的前向链路去交织器具有由两个模计数器构成的地址生成单元。

公开(公告)号：US5274569A

公开(公告)日：1993-12-28

申请号：US776947

申请日：1991-10-15

申请人： Mohit K. Prasad

发明人： Mohit K. Prasad

IPC分类号： G11B20/10 ,  G01R19/04 ,  H03M1/34 ,  G01R29/02

CPC分类号： G01R19/04

摘要： A dual sense non-differencing peak detector locates a peak without introducing unwanted noise components, and also corrects for signal asymmetries. This is accomplished by identifying two sequential sets of two successive samples each. The first set includes samples that fall on each side of a threshold voltage on the rising edge of the signal. The second set includes samples that fall on each side of the threshold on the falling edge of the signal. For each of the two sets of samples, the point at which the signal substantially equals the threshold is found by interpolation. The two threshold points, for a symmetrical signal, fall equidistant from the peak, and hence the peak is easily located as being equidistant therebetween.

摘要翻译： 双重无差分峰值检测器定位峰值而不引入不需要的噪声分量，并且还校正信号不对称性。 这是通过识别两个连续样本的两个连续集合来实现的。 第一组包括在信号上升沿落在阈值电压两侧的采样。 第二组包括在信号下降沿落在阈值两侧的样本。 对于两组样本中的每一组，通过内插发现信号基本上等于阈值的点。 对于对称信号，两个阈值点与峰值等距离，因此峰值容易地位于它们之间的等距离处。

公开(公告)号：US08621322B2

公开(公告)日：2013-12-31

申请号：US12286359

申请日：2008-09-30

申请人： Mohit K. Prasad ,  Clark H. Jarvis

发明人： Mohit K. Prasad ,  Clark H. Jarvis

IPC分类号： H03M13/27 ,  H03M13/53

CPC分类号： H03M13/2771 ,  H03M13/271 ,  H03M13/2714 ,  H03M13/2764 ,  H03M13/2957 ,  H04L1/0066 ,  H04L1/0071

摘要： Methods and corresponding systems in an interleaver include loading K symbol data, in a linear order, into a matrix memory having (R·C) storage locations corresponding R rows and C columns. A sequence of interleaved addresses is produced for reading the K symbol data in an interleaved order from the matrix memory. Next, (R·C)−K interleaved addresses are queued in a first-in-first-out (FIFO) memory. After queuing (R·C)−K interleaved addresses in the FIFO memory, symbol data is output using the interleaved addresses in the FIFO memory to address and output the symbol data in the matrix memory in the interleaved order. The FIFO memory can contain at least 234 memory locations.

摘要翻译： 交织器中的方法和对应系统包括将K个符号数据以线性顺序加载到具有对应于R行和C列的（R·C）存储位置的矩阵存储器中。 产生用于从矩阵存储器以交错顺序读取K个符号数据的交织地址序列。 接下来，（R·C）-K交织地址在先进先出（FIFO）存储器中排队。 在FIFO存储器中排队（R·C）-K交错地址之后，使用FIFO存储器中的交错地址输出符号数据，以交错顺序对矩阵存储器中的符号数据进行寻址和输出。 FIFO存储器可以包含至少234个存储单元。

公开(公告)号：US20130058216A1

公开(公告)日：2013-03-07

申请号：US13224057

申请日：2011-09-01

申请人： Dilip Krishnaswamy ,  Irfan H. Khan ,  Samir S. Soliman ,  Mohit K. Prasad

发明人： Dilip Krishnaswamy ,  Irfan H. Khan ,  Samir S. Soliman ,  Mohit K. Prasad

IPC分类号： H04W76/02 ,  H04W24/00 ,  H04W40/00 ,  H04W52/02

CPC分类号： H04W88/06

摘要： Methods, systems, and devices are described for providing a reconfigurable multi-chip WWAN processing platform on a communications device. The processing platform allows the device to access multiple WWANs and multiple WWAN technologies concurrently. A first multiplexer is communicatively coupled with a number of baseband processing chips. A first baseband processing chip is selectively coupled with a first transceiver and a first UICC module to establish a first connection. A second baseband processing chip is selectively coupled with a second transceiver and a second UICC module to establish a second connection operable concurrently with the first connection. A multiplexer controller performs a configurable search for available networks. One or more networks are selected. The controller selects a specific transceiver for each selected network based on the capabilities of the transceiver. Baseband processing chips that consume less power serve as proxies for other baseband processing chips that consume more power.

摘要翻译： 描述了在通信设备上提供可重新配置的多芯片WWAN处理平台的方法，系统和设备。 处理平台允许设备同时访问多个WWAN和多个WWAN技术。 第一多路复用器与多个基带处理芯片通信地耦合。 第一基带处理芯片选择性地与第一收发器和第一UICC模块耦合以建立第一连接。 第二基带处理芯片选择性地与第二收发器和第二UICC模块耦合，以建立与第一连接同时操作的第二连接。 多路复用器控制器执行可用网络的可配置搜索。 选择一个或多个网络。 控制器根据收发器的能力为每个选定的网络选择一个特定的收发器。 消耗更少功率的基带处理芯片可以用作消耗更多功率的其他基带处理芯片的代理。

公开(公告)号：US06748561B2

公开(公告)日：2004-06-08

申请号：US10325495

申请日：2002-12-20

申请人： Mohit K. Prasad

发明人： Mohit K. Prasad

IPC分类号： G11C2900

CPC分类号： H03M13/2785 ,  H03M13/2764

摘要： A method and apparatus is provided for interleaving and de-interleaving frame symbols using a single memory buffer. Input frame symbols are read out in an interleaved sequence (or de-interleaved sequence) on a symbol by symbol basis. Frame symbols following the input frame symbols are written into memory locations from where the input frame symbols were read.

摘要翻译： 提供了一种用于使用单个存储器缓冲器对帧符号进行交织和解交织的方法和装置。 以符号为单位的交错序列（或解交织序列）读出输入帧符号。 输入帧符号之后的帧符号被写入从其中读取输入帧符号的存储器位置。

公开(公告)号：US06560212B1

公开(公告)日：2003-05-06

申请号：US09270916

申请日：1999-03-16

申请人： Mohit K. Prasad ,  Xiao-An Wang

发明人： Mohit K. Prasad ,  Xiao-An Wang

IPC分类号： H04B7216

CPC分类号： H04B1/70756 ,  H03K3/84 ,  H04J13/10

摘要： An offset sequence generator generates an offset sequence from a reference sequence, the offset sequence being a cyclic-shifted version of the reference sequence. The reference sequence is a deBruijn sequence formed from a pseudo-noise (PN) sequence augmented with an insert-bit, the insert-bit being inserted at a rollover state of the PN sequence. The offset generator includes a decision circuit that selects values of either the reference sequence or a delayed reference sequence as an input to a mask circuit. The mask circuit applies masks so as to generate the PN sequence of the offset sequence. The decision circuit also detects the rollover state of the PN sequence of the offset sequence, and inserts the insert-bit so as to provide the offset sequence.

摘要翻译： 偏移序列生成器从参考序列生成偏移序列，偏移序列是参考序列的循环移位版本。 参考序列是由扩展有插入位的伪噪声（PN）序列形成的deBruijn序列，插入位以PN序列的翻转状态插入。 偏移发生器包括选择参考序列或延迟参考序列的值作为掩码电路的输入的判定电路。 掩模电路应用掩模以产生偏移序列的PN序列。 判定电路还检测偏移序列的PN序列的翻转状态，并插入插入位以提供偏移序列。

公开(公告)号：US20120260008A1

公开(公告)日：2012-10-11

申请号：US13081713

申请日：2011-04-07

申请人： Vaibhav Kumar ,  Mark A. Landguth ,  Mohit K. Prasad ,  Erez Tsidon ,  Shailesh Maheshwari ,  Rashmi Char ,  Robert C. Coleman

发明人： Vaibhav Kumar ,  Mark A. Landguth ,  Mohit K. Prasad ,  Erez Tsidon ,  Shailesh Maheshwari ,  Rashmi Char ,  Robert C. Coleman

IPC分类号： G06F3/00

CPC分类号： G06F13/385

摘要： One embodiment of the invention comprises a non-transitory, tangible computer readable storage medium encoded with processor readable instructions to perform a method of transferring SDIO data. One method comprises buffering multiple IP packets to transfer from one of a SDCC host and a SDIO client to the other of the SDCC host and the SDIO client. A multiplexing header is attached to each of the multiple IP packets and one of at least one SDIO read command and at least one SDIO write command issued. The multiple IP packets are then transferred in a single SDIO transfer between the one of a SDCC host and a SDIO client to the other of the SDCC host and the SDIO client.

摘要翻译： 本发明的一个实施例包括编码有处理器可读指令以执行传送SDIO数据的方法的非暂时有形的计算机可读存储介质。 一种方法包括缓冲多个IP分组以从SDCC主机和SDIO客户端之一传送到SDCC主机和SDIO客户端中的另一个。 复用报头附加到多个IP分组中的每一个，并且发出至少一个SDIO读取命令和至少一个SDIO写入命令中的一个。 然后，将多个IP分组以SDCC主机和SDIO客户端之一的单个SDIO传输方式传输到SDCC主机和SDIO客户端的另一个。

公开(公告)号：US07404139B2

公开(公告)日：2008-07-22

申请号：US11040861

申请日：2005-01-21

申请人： Mohit K. Prasad ,  Nitin Vig ,  Arnab K. Mitra ,  Amrit P. Singh ,  Gaurav Davra

发明人： Mohit K. Prasad ,  Nitin Vig ,  Arnab K. Mitra ,  Amrit P. Singh ,  Gaurav Davra

IPC分类号： H03M13/03

CPC分类号： H03M13/4169 ,  H03M13/3961 ,  H03M13/6502

摘要： A Maximum Likelihood Sequence Estimation (MLSE) decoder that decodes an encoded sequence of data symbols includes a branch metric unit for computing branch metrics for each trellis stage of the encoded sequence, a path metric unit for computing a path metric for each trellis stage using the computed branch metrics, and an M-at-a-time traceback unit for performing an M-at-a-time traceback operation using the computed path metrics. The M-at-a-time traceback operation generates M decoded data symbols in a single M-at-a-time traceback operation.

摘要翻译： 对编码的数据符号序列进行解码的最大似然序列估计（MLSE）解码器包括用于计算编码序列的每个网格级的分支度量的分支度量单位，用于使用所述编码序列计算每个网格级的路径度量的路径度量单位 计算的分支度量，以及M-at-time追溯单元，用于使用所计算的路径度量来执行M-at-time追溯操作。 M-at-time追溯操作在单次M-at-time追溯操作中生成M个解码的数据符号。