摘要:
A wafer level package for a surface acoustic wave device and a fabrication method thereof include a SAW device formed with a SAW element on an upper surface of a device wafer; a cap wafer joined on an upper part of the SAW element; a cavity part housing the SAW element between the cap wafer and the SAW device; a cap pad formed on an upper surface of the cap wafer; and a metal line formed to penetrate through the cap wafer to electrically connect the cap pad and the SAW element, the device wafer and the cap wafer being made of the same materials.
摘要:
A multi stack packaging chip and a method of manufacturing the chip are provided. The method includes forming at least one second circuit element on a first wafer; forming a second wafer having a cavity and a one third circuit element formed opposite to the cavity; forming a solder on the second wafer; and combining the second wafer with the first wafer so that the second circuit element and the cavity correspond. The chip includes a flip-chip packaged chip in which a first circuit element is packaged using a first wafer; a second circuit element formed on the first wafer; a second wafer having a cavity and combined with the first wafer so that the cavity and the second circuit element correspond; a third circuit element formed on the second wafer; and a solder formed on the second wafer, the solder electrically coupling the second wafer to a packaging substrate.
摘要:
A fabrication method of a packaging substrate includes the steps of: forming a recess by etching a predetermined area of a lower surface of a substrate; depositing a seed layer on an upper surface of the substrate; in the recess, etching predetermined area(s) of the lower surface of the substrate and forming at least one via hole that reaches the seed layer; and plating the inside of the via hole by using the seed layer, and forming electrode(s) for electrically coupling the upper and lower parts of the substrate. First and second pads coupled to the electrode(s) may be formed on the upper and lower parts of the substrate, respectively. Thus, using the second pads as bonding materials, the packaging process becomes easier, which resultantly simplifies the fabrication process of the packaging substrate and the packaging process.
摘要:
A fabrication method of a packaging substrate includes the steps of: forming a recess by etching a predetermined area of a lower surface of a substrate; depositing a seed layer on an upper surface of the substrate; in the recess, etching predetermined area(s) of the lower surface of the substrate and forming at least one via hole that reaches the seed layer; and plating the inside of the via hole by using the seed layer, and forming electrode(s) for electrically coupling the upper and lower parts of the substrate. First and second pads coupled to the electrode(s) may be formed on the upper and lower parts of the substrate, respectively. Thus, using the second pads as bonding materials, the packaging process becomes easier, which resultantly simplifies the fabrication process of the packaging substrate and the packaging process.
摘要:
A wafer level packaging cap for covering a device wafer with a device thereon and a fabrication method thereof are provided. The method includes operations of forming a plurality of connection grooves on a wafer, forming a seed layer on the connection grooves, forming connection parts by filling the connection grooves with a metal material, forming cap pads on a top surface of the wafer to be electrically connected to the connection parts, bonding a supporting film with the top surface of the wafer on which the cap pads are formed, forming a cavity on a bottom surface of the wafer to expose the connection parts through the cavity, and forming metal lines on the bottom surface of the wafer to be electrically connected to the connection parts.
摘要:
A multi stack packaging chip and a method of manufacturing the chip are provided. The method includes forming at least one second circuit element on a first wafer; forming a second wafer having a cavity and a one third circuit element formed opposite to the cavity; forming a solder on the second wafer; and combining the second wafer with the first wafer so that the second circuit element and the cavity correspond. The chip includes a flip-chip packaged chip in which a first circuit element is packaged using a first wafer; a second circuit element formed on the first wafer; a second wafer having a cavity and combined with the first wafer so that the cavity and the second circuit element correspond; a third circuit element formed on the second wafer; and a solder formed on the second wafer, the solder electrically coupling the second wafer to a packaging substrate.
摘要:
A wafer level package for a surface acoustic wave device and a fabrication method thereof include a SAW device formed with a SAW element on an upper surface of a device wafer; a cap wafer joined on an upper part of the SAW element; a cavity part housing the SAW element between the cap wafer and the SAW device; a cap pad formed on an upper surface of the cap wafer; and a metal line formed to penetrate through the cap wafer to electrically connect the cap pad and the SAW element, the device wafer and the cap wafer being made of the same materials.
摘要:
A wafer level packaging cap for covering a device wafer with a device thereon and a fabrication method thereof are provided. The method includes operations of forming a plurality of connection grooves on a wafer, forming a seed layer on the connection grooves, forming connection parts by filling the connection grooves with a metal material, forming cap pads on a top surface of the wafer to be electrically connected to the connection parts, bonding a supporting film with the top surface of the wafer on which the cap pads are formed, forming a cavity on a bottom surface of the wafer to expose the connection parts through the cavity, and forming metal lines on the bottom surface of the wafer to be electrically connected to the connection parts.
摘要:
A cap wafer including a cavity, a packaged semiconductor including the cap wafer, and a method of fabricating the cap wafer. The cap wafer includes a cavity formed in an area of a lower surface of the cap wafer; and at least one feed-through penetrating through upper and lower surfaces of the cap wafer so as to be connected to the cavity. The packaged semiconductor includes a base wafer including an upper surface including an area in which a circuit device is formed; a cap wafer including a lower surface including an area in which a cavity having a predetermined size is formed, the cap wafer being combined with the base wafer to position the circuit device in the cavity so as to package the circuit device; and at least one feed-through penetrating through upper and lower portions of the cap wafer so as to be connected to the cavity and electrically connected to the circuit device.
摘要:
A micro-mirror device package including a micro-mirror device; a substrate, on which the micro-mirror device is mounted; and a window lid mounted on the substrate to cover the micro-mirror device. The window lid has a light transmitting part, which is sloped in relation to the micro-mirror device, and through which laser beams are transmitted to the micro-mirror device, and supporting parts downwardly extending from the light transmitting part. When a laser beam is inputted, the package separates the laser beam from noise beams, thereby improving the quality of image on a screen. By fabricating an array of window lids which correspond to micro-mirror devices, respectively, it is possible to fabricate the above-mentioned micro-mirror device package through a batch process performed in terms of a wafer size.