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    Packaging chip and packaging method thereof
    3.
    发明申请
    Packaging chip and packaging method thereof 失效
    包装芯片及其包装方法

    公开(公告)号：US20060273444A1

    公开(公告)日：2006-12-07

    申请号：US11390220

    申请日：2006-03-28

    申请人： Kyu-dong Jung ,  Woon-bae Kim ,  In-sang Song ,  Moon-chul Lee ,  Jun-sik Hwang ,  Suk-jin Ham

    发明人： Kyu-dong Jung ,  Woon-bae Kim ,  In-sang Song ,  Moon-chul Lee ,  Jun-sik Hwang ,  Suk-jin Ham

    IPC分类号： H01L23/48

    CPC分类号： H01L23/055 ,  H01L23/04 ,  H01L27/14618 ,  H01L2224/16

    摘要： A packaging chip in which a circuit module is packaged and a method of packaging a circuit module are provided. The packaging chip includes a base wafer; a circuit module on the base wafer; a packaging wafer having a cavity and combined with the base wafer so that the circuit module fits inside the cavity; a connecting electrode connecting upper and lower surfaces of the cavity; and a seed layer between the connecting electrode and the packaging wafer. The method includes etching a lower surface of the packaging wafer to form a cavity, stacking a metal layer in an area of the lower surface, combining the base wafer with the packaging wafer, polishing the packaging wafer, forming a viahole through the packaging wafer, stacking a seed layer on the packaging wafer, plating the inside of the viahole, removing the seed layer and forming an electrode.

    摘要翻译： 提供电路模块封装的封装芯片和封装电路模块的方法。 包装芯片包括基底晶片; 基底晶片上的电路模块; 封装晶片，其具有空腔并与所述基底晶片组合，使得所述电路模块装配在所述腔内; 连接所述空腔的上表面和下表面的连接电极; 以及连接电极和封装晶片之间的晶种层。 该方法包括蚀刻封装晶片的下表面以形成空腔，在下表面的区域中堆叠金属层，将基底晶片与封装晶片组合，抛光封装晶片，通过封装晶片形成通孔， 将种子层堆叠在包装晶片上，电镀通孔内部，去除种子层并形成电极。

    Wafer level packaging cap and fabrication method thereof
    5.
    发明授权
    Wafer level packaging cap and fabrication method thereof 有权
    晶圆级封装盖及其制造方法

    公开(公告)号：US07579685B2

    公开(公告)日：2009-08-25

    申请号：US11339500

    申请日：2006-01-26

    申请人： Moon-chul Lee ,  Woon-bae Kim ,  Kae-dong Back ,  Qian Wang ,  Jun-sik Hwang ,  Kyu-dong Jung

    发明人： Moon-chul Lee ,  Woon-bae Kim ,  Kae-dong Back ,  Qian Wang ,  Jun-sik Hwang ,  Kyu-dong Jung

    IPC分类号： H01L23/12 ,  H01L23/043

    CPC分类号： B81C1/00301 ,  B81B2207/095 ,  H01L21/76898 ,  H01L23/04 ,  H01L23/10 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A wafer level packaging cap and method thereof for a wafer level packaging are provided. The wafer level packaging cap covering a device wafer with a device thereon, includes a cap wafer having on a bottom surface a cavity providing a space for receiving the device, and integrally combined with the device wafer, a plurality of metal lines formed on the bottom surface of the cap wafer to correspond to a plurality of device pads formed on the device wafer to be electrically connected to the device, a plurality of buffer portions connected to the plurality of metal lines and comprising a buffer wafer with a plurality of grooves and a metal filled in the plurality of grooves, a plurality of connection rods electrically connected to the plurality of buffer portions and penetrating the cap wafer from a top portion of the buffer portion, and a plurality of cap pads formed on a top surface of the cap wafer and electrically connected to a plurality of connection rods.

    摘要翻译： 提供了一种用于晶片级封装的晶片级封装盖及其方法。 覆盖其上具有器件的器件晶片的晶片级封装盖包括盖晶片，其在底表面上具有提供用于接收器件的空间并与器件晶片整体结合的空腔，形成在底部的多个金属线 盖片晶片的表面对应于形成在器件晶片上以电连接到器件的多个器件焊盘，多个缓冲部分连接到多个金属线并且包括具有多个沟槽的缓冲晶片和 填充在所述多个槽中的金属，多个连接杆，电连接到所述多个缓冲部分，并且从所述缓冲部分的顶部穿透所述盖片;以及形成在所述盖片的顶表面上的多个帽垫 并且电连接到多个连接杆。

    Packaging chip and packaging method thereof
    6.
    发明授权
    Packaging chip and packaging method thereof 失效
    包装芯片及其包装方法

    公开(公告)号：US07408257B2

    公开(公告)日：2008-08-05

    申请号：US11390220

    申请日：2006-03-28

    申请人： Kyu-dong Jung ,  Woon-bae Kim ,  In-sang Song ,  Moon-chul Lee ,  Jun-sik Hwang ,  Suk-jin Ham

    发明人： Kyu-dong Jung ,  Woon-bae Kim ,  In-sang Song ,  Moon-chul Lee ,  Jun-sik Hwang ,  Suk-jin Ham

    IPC分类号： H01L23/04

    CPC分类号： H01L23/055 ,  H01L23/04 ,  H01L27/14618 ,  H01L2224/16

    摘要： A packaging chip in which a circuit module is packaged and a method of packaging a circuit module are provided. The packaging chip includes a base wafer; a circuit module on the base wafer; a packaging wafer having a cavity and combined with the base wafer so that the circuit module fits inside the cavity; a connecting electrode connecting upper and lower surfaces of the cavity; and a seed layer between the connecting electrode and the packaging wafer. The method includes etching a lower surface of the packaging wafer to form a cavity, stacking a metal layer in an area of the lower surface, combining the base wafer with the packaging wafer, polishing the packaging wafer, forming a viahole through the packaging wafer, stacking a seed layer on the packaging wafer, plating the inside of the viahole, removing the seed layer and forming an electrode.

    摘要翻译： 提供电路模块封装的封装芯片和封装电路模块的方法。 包装芯片包括基底晶片; 基底晶片上的电路模块; 封装晶片，其具有空腔并与所述基底晶片组合，使得所述电路模块装配在所述腔内; 连接所述空腔的上表面和下表面的连接电极; 以及连接电极和封装晶片之间的晶种层。 该方法包括蚀刻封装晶片的下表面以形成空腔，在下表面的区域中堆叠金属层，将基底晶片与封装晶片组合，抛光封装晶片，通过封装晶片形成通孔， 将种子层堆叠在包装晶片上，电镀通孔内部，去除种子层并形成电极。

    IMAGE FORMING ELEMENT AND FABRICATING METHOD THEREOF, AND IMAGE FORMING APPARATUS HAVING THE IMAGE FORMING ELEMENT
    9.
    发明申请
    IMAGE FORMING ELEMENT AND FABRICATING METHOD THEREOF, AND IMAGE FORMING APPARATUS HAVING THE IMAGE FORMING ELEMENT 审中-公开
    图像形成元件及其制作方法，以及具有图像形成元件的图像形成装置

    公开(公告)号：US20080252712A1

    公开(公告)日：2008-10-16

    申请号：US11855381

    申请日：2007-09-14

    申请人： Su-ho Shin ,  Chang-youl Moon ,  Ki-hwan Kwon ,  Yu-man Kim ,  Kyu-dong Jung

    发明人： Su-ho Shin ,  Chang-youl Moon ,  Ki-hwan Kwon ,  Yu-man Kim ,  Kyu-dong Jung

    IPC分类号： B41J2/39

    CPC分类号： G03G15/348 ,  G03G2217/0075

    摘要： An image forming element includes a drum body including a plurality of conductive layers and a plurality of insulating layers stacked on one another in an alternate pattern, in which a portion of each of the conductive layers extends towards a cavity defined within the conductive layers to form a plurality of electrodes, and a control unit disposed in the cavity, and including a plurality of electrode pads corresponding to the electrodes to provide an electrical connection to the respective electrodes. Structure and processes to fabricate an image forming element are simplified, and fabricating cost can be reduced.

    摘要翻译： 图像形成元件包括：鼓本体，其包括多个导电层和多个以交替图案彼此堆叠的绝缘层，其中每个导电层的一部分朝着限定在导电层内的空腔延伸以形成 多个电极和设置在空腔中的控制单元，并且包括对应于电极的多个电极焊盘以提供到各个电极的电连接。 制造图像形成元件的结构和工艺被简化，并且可以降低制造成本。

    Wafer level packaging cap and fabrication method thereof
    10.
    发明申请
    Wafer level packaging cap and fabrication method thereof 有权
    晶圆级封装盖及其制造方法

    公开(公告)号：US20070164410A1

    公开(公告)日：2007-07-19

    申请号：US11491086

    申请日：2006-07-24

    申请人： Yong-sung Kim ,  Woon-Bae Kim ,  Kyu-dong Jung ,  Chang-seung Lee

    发明人： Yong-sung Kim ,  Woon-Bae Kim ,  Kyu-dong Jung ,  Chang-seung Lee

    IPC分类号： H01L23/02

    CPC分类号： B81C1/00301 ,  B81B2207/095 ,  B81C2203/0118 ,  H01L23/04 ,  H01L2924/01079 ,  H01L2924/16235

    摘要： A fabrication method of a wafer level packaging cap for covering a device wafer provided with a device thereon, includes forming an insulating layer on a wafer; removing a predetermined part of the insulating layer and exposing an upper surface of the wafer; forming a cap pad extending from an upper surface and the exposed surface of the wafer; forming a cavity on a lower surface of the wafer corresponding to the cap pad; etching a bottom surface of the cavity and exposing the cap pad which is connected to the wafer through the cavity; and forming metal lines extending from the lower surface of the wafer and the cavity, to electrically connect the cap pad which is exposed through the cavity.

    摘要翻译： 一种用于覆盖其上具有器件的器件晶片的晶片级封装帽的制造方法，包括在晶片上形成绝缘层; 去除所述绝缘层的预定部分并暴露所述晶片的上表面; 形成从所述晶片的上表面和所述暴露表面延伸的盖焊盘; 在与所述盖垫对应的所述晶片的下表面上形成空腔; 蚀刻空腔的底表面并暴露通过空腔连接到晶片的盖垫; 以及形成从所述晶片的下表面和所述腔延伸的金属线，以电连接通过所述空腔暴露的所述盖垫。