公开(公告)号：US07782237B2

公开(公告)日：2010-08-24

申请号：US12139299

申请日：2008-06-13

申请人： Mostafa Ronaghi ,  Ali Agah

发明人： Mostafa Ronaghi ,  Ali Agah

IPC分类号： H03M1/66

CPC分类号： H03M3/46 ,  H03M3/45 ,  H03M3/452

摘要： An error-corrected representation of an input signal, such as a bioluminescence signal, is generated. An analog representation of the input signal is oversampled and quantized to provide a first-stage digital output and a residual error. The residual error is provided as a second-stage digital output using successive approximation. The first-stage and second-stage digital outputs are used to generate an error-corrected representation of the bioluminescence signal.

摘要翻译： 产生诸如生物发光信号的输入信号的纠错表示。 输入信号的模拟表示被过采样和量化，以提供第一级数字输出和残差。 剩余误差被提供为使用逐次逼近的第二级数字输出。 第一级和第二级数字输出用于产生生物发光信号的纠错表示。

公开(公告)号：US20090309773A1

公开(公告)日：2009-12-17

申请号：US12139299

申请日：2008-06-13

申请人： Mostafa Ronaghi ,  Ali Agah

发明人： Mostafa Ronaghi ,  Ali Agah

IPC分类号： H03M1/12 ,  H03M3/00

CPC分类号： H03M3/46 ,  H03M3/45 ,  H03M3/452

摘要： An error-corrected representation of an input signal, such as a bioluminescence signal, is generated. An analog representation of the input signal is oversampled and quantized to provide a first-stage digital output and a residual error. The residual error is provided as a second-stage digital output using successive approximation. The first-stage and second-stage digital outputs are used to generate an error-corrected representation of the bioluminescence signal.

摘要翻译： 产生诸如生物发光信号的输入信号的纠错表示。 输入信号的模拟表示被过采样和量化以提供第一级数字输出和残差。 剩余误差被提供为使用逐次逼近的第二级数字输出。 第一级和第二级数字输出用于产生生物发光信号的纠错表示。

公开(公告)号：US07852248B1

公开(公告)日：2010-12-14

申请号：US12331369

申请日：2008-12-09

申请人： Mansour Keramat ,  Ali Agah ,  Ali Tabatabaei

发明人： Mansour Keramat ,  Ali Agah ,  Ali Tabatabaei

IPC分类号： H03M3/00

CPC分类号： H03M3/372 ,  H03M3/458

摘要： In one embodiment of the present invention, at least at one stage of a Sigma-Delta analog-to-digital converter (ADC) is disclosed to include means for receiving a voltage at least one of the inputs of an operational amplifier, the operational amplifier having at least one output coupled to the at least one of the inputs via an at least one integration capacitor, means for transforming the voltage to a current and means for integrating the current on the at least one of the integration capacitors, during integration time and varying the resistance of at least one of a variable resistors coupled to the operational amplifier during integration time.

摘要翻译： 在本发明的一个实施例中，公开了Sigma-Delta模数转换器（ADC）的至少一个阶段，以包括用于接收运算放大器的至少一个输入的电压的装置，运算放大器 具有经由至少一个积分电容器耦合到所述至少一个输入的至少一个输出，用于将所述电压转换为电流的装置，以及用于在所述积分时间期间将所述电流集成在所述至少一个所述积分电容器上的装置;以及 在积分时间期间改变耦合到运算放大器的可变电阻器中的至少一个的电阻。