-
公开(公告)号：US20190253068A1
公开(公告)日：2019-08-15
申请号：US16392899
申请日：2019-04-24
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Kimmo KOLI
Abstract: A receiver is described, the receiver comprising an ABB filter stage, an ADC stage. The ABB filter stage comprises an ABB filter stage input configured to receive an analog baseband, BB, signal and an ABB filter stage output configured to provide a filtered analog BB signal. The ADC stage comprises an ADC stage input configured to receive the filtered analog BB signal and an ADC stage output configured to provide a digital BB signal. The ADC stage comprises an ADC comprising an ADC input configured to receive the filtered analog BB signal or a signal derived therefrom as an ADC input signal, and wherein the ADC is configured to perform an analog-to-digital, A/D, conversion of the ADC input signal to derive the digital BB signal.
-
2.发明申请DELTA SIGMA MODULATOR FOR SHAPING NOISE AND AUDIO CODEC HAVING THE SAME 有权用于形成噪声的DELTA SIGMA调制器和具有该噪声的音频编码公开(公告)号：US20170019123A1
公开(公告)日：2017-01-19
申请号：US15097715
申请日：2016-04-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Mooyeol Choi , Hyungdong Roh , Bai-Sun Kong , Sunwoo Kwon , Myung-Jin Lee
Abstract: A delta-sigma modulator includes a loop filter, a quantizer configured to change an analog output signal into a digital signal, and a digital-to-analog converter configured to receive the digital signal and including a first capacitor and a second capacitor. In a first sampling period, the first capacitor is discharged, and at the same time, the second capacitor is charged with a reference voltage. In a second sampling period, the digital signal includes noise caused by a clock jitter, the first capacitor is charged with a reference voltage, and the second capacitor is discharged and generates a charge corresponding to the noise. In a next first sampling period, the first capacitor is discharged, and at the same time, the second capacitor generates a noise current corresponding to the noise using the charge and is charged with a reference voltage.
Abstract translation: Δ-Σ调制器包括环路滤波器，被配置为将模拟输出信号改变为数字信号的量化器，以及被配置为接收数字信号并包括第一电容器和第二电容器的数/模转换器。 在第一采样周期中，第一电容器被放电，同时第二电容器被充以基准电压。 在第二采样周期中，数字信号包括由时钟抖动引起的噪声，第一电容器用参考电压充电，并且第二电容器被放电并产生对应于噪声的电荷。 在接下来的第一采样周期中，第一电容器被放电，并且同时第二电容器使用电荷产生与噪声相对应的噪声电流并且对基准电压进行充电。
-
公开(公告)号：US20150171887A1
公开(公告)日：2015-06-18
申请号：US14548377
申请日：2014-11-20
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Takashi OKUDA
IPC: H03M3/00
Abstract: A delta-sigma modulator is configured to feedback an output signal of a quantizer to an input of an integrator, and also feedback to the input of the integrator a differentiated error signal representing derivative of quantization error caused by the quantizer.
Abstract translation: Δ-Σ调制器被配置为将量化器的输出信号反馈到积分器的输入，并且还向积分器的输入反馈表示由量化器引起的量化误差的微分误差信号。
-
4.发明授权System and method for correcting phase noise in digital-to-analog converter or analog-to-digital converter 有权用于校正数模转换器或模数转换器中的相位噪声的系统和方法公开(公告)号：US08483856B2
公开(公告)日：2013-07-09
申请号：US12783290
申请日：2010-05-19
Applicant: Rahmi Hezar , Baher Haroun
Inventor： Rahmi Hezar , Baher Haroun
IPC: G06F17/00
Abstract: A circuit includes a digital oscillator, a phase lock loop (PLL), a digital signal generator, a correction circuit and a digital-to-analog converter DAC (DAC). The digital oscillator can output a reference clock signal. The PLL can output a system clock signal based on the reference clock signal. The digital signal generator can output a digital signal based on the system clock signal. The correction circuit can output a pre-distorted signal based on the reference clock signal, the system clock signal and the digital signal. The DAC can output an analog signal based on the pre-distorted signal and the system clock signal.
Abstract translation: 电路包括数字振荡器，锁相环（PLL），数字信号发生器，校正电路和数模转换器DAC（DAC）。 数字振荡器可以输出参考时钟信号。 PLL可以基于参考时钟信号输出系统时钟信号。 数字信号发生器可以根据系统时钟信号输出数字信号。 校正电路可以基于参考时钟信号，系统时钟信号和数字信号输出预失真信号。 DAC可以根据预失真信号和系统时钟信号输出模拟信号。
-
5.发明申请SYSTEM AND METHOD FOR CORRECTING PHASE NOISE IN DIGITAL-TO-ANALOG CONVERTER OR ANALOG-TO-DIGITAL CONVERTER 有权用于校正数字到模拟转换器或模拟数字转换器中的相位噪声的系统和方法公开(公告)号：US20110285433A1
公开(公告)日：2011-11-24
申请号：US12783290
申请日：2010-05-19
Applicant: Rahmi Hezar , Baher Haroun
Inventor： Rahmi Hezar , Baher Haroun
IPC: H03L7/08
Abstract: A circuit includes a digital oscillator, a phase lock loop (PLL), a digital signal generator, a correction circuit and a digital-to-analog converter DAC (DAC). The digital oscillator can output a reference clock signal. The PLL can output a system clock signal based on the reference clock signal. The digital signal generator can output a digital signal based on the system clock signal. The correction circuit can output a pre-distorted signal based on the reference clock signal, the system clock signal and the digital signal. The DAC can output an analog signal based on the pre-distorted signal and the system clock signal.
Abstract translation: 电路包括数字振荡器，锁相环（PLL），数字信号发生器，校正电路和数模转换器DAC（DAC）。 数字振荡器可以输出参考时钟信号。 PLL可以基于参考时钟信号输出系统时钟信号。 数字信号发生器可以根据系统时钟信号输出数字信号。 校正电路可以基于参考时钟信号，系统时钟信号和数字信号输出预失真信号。 DAC可以根据预失真信号和系统时钟信号输出模拟信号。
-
Patent Agency Ranking
公开(公告)号：US07142143B2
公开(公告)日：2006-11-28
申请号：US11067602
申请日：2005-02-26
Applicant: Dieter Draxelmayr
Inventor： Dieter Draxelmayr
IPC: H03M3/00
Abstract: Time-continuous sigma/delta analog-to-digital converter for converting an analog input signal into a digital output signal (D), having at least one analog filter (3) which filters the analog input signal present at a signal input (2) of the analog filter (3), a quantizer (12) which is clocked by a clock signal (CLK) and quantizes the filtered analog signal, output by the analog filter (3), in order to generate the digital output signal (D), and having at least one reference capacitor (28) which can be continuously charged to a reference voltage (VREF) by a current source (31) for displacing a constant charge (Q) to/from the analog filter (3), such that no voltage jumps occur at the analog filter (3).
Abstract translation: 一种用于将模拟输入信号转换为数字输出信号（D）的时间连续的Σ/Δ模数转换器，具有至少一个模拟滤波器（3），其对存在于信号输入端（2）的模拟输入信号进行滤波， 模拟滤波器（3）的量化器（12），由时钟信号（CLK）计时并量化由模拟滤波器（3）输出的经滤波的模拟信号，以产生数字输出信号（D） ，并且具有至少一个参考电容器（28），其可以通过电流源（31）连续地充电到参考电压（V SUB REF），用于将恒定电荷（Q）移位到/ 模拟滤波器（3），使得在模拟滤波器（3）处不发生电压跳变。
-
公开(公告)号：US06734816B2
公开(公告)日：2004-05-11
申请号：US10408238
申请日：2003-04-08
Applicant: Yasuo Morimoto , Toshio Kumamoto , Takashi Okuda
Inventor： Yasuo Morimoto , Toshio Kumamoto , Takashi Okuda
IPC: H03M166
Abstract: A D/A converter including a plurality of potential generating sections. They each receive a 1-bit signal from one of an input terminal and delay circuit, and a clock signal or inverted clock signal from an input section or inverter for inverting the clock signal. When the clock signal or inverted clock signal is at a first signal level, they generate a first reference potential or second reference potential in response to the signal level of the 1-bit signal. When the clock signal or inverted clock signal is at the second level, they generate an intermediate potential between the first and second reference potentials. The potentials generated by the plurality of potential generating sections are combined by a combining section. The D/A converter can improve resistance to jitter, and to simplify the configuration of a post-stage filter circuit.
Abstract translation: 一种D / A转换器，包括多个电位产生部分。 它们各自从输入端和延迟电路之一接收1位信号，以及来自用于反相时钟信号的输入部分或反相器的时钟信号或反相时钟信号。 当时钟信号或反相时钟信号处于第一信号电平时，它们响应于1位信号的信号电平而产生第一参考电位或第二参考电位。 当时钟信号或反相时钟信号处于第二电平时，它们在第一和第二参考电位之间产生中间电位。 由多个电位产生部分产生的电位由组合部分组合。 D / A转换器可以提高抗抖动性，并简化后级滤波电路的配置。
-
8.发明申请Method and system for adjusting the step clock of a delta-sigma transformer and/or switched capacitor filter 失效用于调整delta-sigma变压器和/或开关电容滤波器的步进时钟的方法和系统公开(公告)号：US20040037386A1
公开(公告)日：2004-02-26
申请号：US10399790
申请日：2003-04-22
Inventor： Heikki Laamanen
IPC: H03K021/00
CPC classification number: H03L7/0993 , H03H19/004 , H03M3/372 , H03M3/498
Abstract: The invention relates to a method and system for implementing a digitally controlled sample and timing clock in a system performing analog and digital signal processing. According to the method, as the timing clock of the digital signal processing is used a clock with a controllable frequency such that said digital signal processing can have a factions suited for controlling the frequency of said timing clock, and the conversion of the signal is performed in synchronism with the timing clock of the digital signal processing operation when a delta-sigma converter or a switched-capacitor filter device is employed. According to the invention, the timing and sample clocks are generated by dividing a fixed-frequency clock operating at a frequency substantially higher than that of said timing/sample clock by a digital divider of an integer division factor whose division factor is controlled by means of an at least second-order delta-sigma modulator capable of delivering an output signal of two values so that one of the modulator output signal values selects the division factor to be N while the other value selects the division factor to be Nnull1, and, further, the delta-sigma modulator controlling the integer-factor divider is adapted to be clocked by the timing signal generated by said integer-factor divider.
Abstract translation: 本发明涉及在执行模拟和数字信号处理的系统中实现数字控制采样和定时时钟的方法和系统。 根据该方法，由于数字信号处理的定时时钟使用具有可控频率的时钟，使得所述数字信号处理可以具有适合于控制所述定时时钟的频率的系数，并且执行信号的转换 与采用Δ-Σ转换器或开关电容滤波器装置的数字信号处理操作的定时时钟同步。 根据本发明，定时和采样时钟是通过将工作在基本上高于所述定时/采样时钟的频率的固定频率时钟除以整数分频因子的数字分频器而产生的，其分频因子通过 能够输出两个值的输出信号的至少二阶Δ-Σ调制器，使得一个调制器输出信号值选择分频因子为N，而另一个值选择分频因子为N + 1，以及 此外，控制整数因子分频器的Δ-Σ调制器适于由所述整数因子分频器产生的定时信号计时。
-
公开(公告)号：US5625359A
公开(公告)日：1997-04-29
申请号：US466215
申请日：1995-06-06
Applicant: James Wilson , Ronald A. Cellini , James M. Sobol
Inventor： James Wilson , Ronald A. Cellini , James M. Sobol
Abstract: A method and apparatus for analog-to-digital conversion using sigma-delta modulation of the temporal spacing between digital samples are provided. The method and apparatus include sigma-delta modulation of the time-base such that errors produced by non-uniform sampling are frequency-shaped to a high frequency region where they are reduced by conventional digital filtering techniques. In one embodiment, a sigma-delta ADC receives an analog input signal and converts the analog input signal to digital samples at an oversampling rate. A decimator, coupled to the sigma-delta ADC, receives the digital samples and decimates the digital samples to produce the digital samples at a preselected output sample rate, less than the oversampling rate. An ADC sample rate control circuit, coupled to the ADC, receives a frequency select signal representing the preselected output sample rate, and produces a noise-shaped clock signal for controlling operation of the ADC at the oversampling rate. The control circuit includes a sigma-delta modulator for sigma-delta modulating the frequency select signal. A randomizer/suppressor circuit, under control of the output of the sigma-delta modulator, receives an input clock signal and adjusts the frequency of the clock signal to produce a noise-shaped clock signal for controlling the oversampling rate of the ADC.
Abstract translation: 提供了一种使用数字样本之间的时间间隔的Σ-Δ调制进行模数转换的方法和装置。 该方法和装置包括时基的Σ-Δ调制，使得由非均匀采样产生的误差是频率形状的高频区域，它们被传统的数字滤波技术所减少。 在一个实施例中，Σ-ΔADC接收模拟输入信号，并以过采样速率将模拟输入信号转换成数字采样。 耦合到Σ-ΔADC的抽取器接收数字采样并抽取数字采样，以预选的输出采样率产生数字样本，小于过采样率。 耦合到ADC的ADC采样率控制电路接收表示预选输出采样率的频率选择信号，并产生用于以过采样速率控制ADC的操作的噪声形状的时钟信号。 控制电路包括用于Σ-Δ调制频率选择信号的Σ-Δ调制器。 在Σ-Δ调制器的输出控制下的随机化/抑制电路接收输入时钟信号并调节时钟信号的频率，以产生用于控制ADC过采样速率的噪声形时钟信号。
-
公开(公告)号：US12088324B2
公开(公告)日：2024-09-10
申请号：US17820975
申请日：2022-08-19
Applicant: Infineon Technologies AG
Inventor： Ahmed Abdelaal , John G. Kauffman , Maurits Ortmanns , Takashi Miki
IPC: H03M3/00
Abstract: In accordance with an embodiment, a delta-sigma modulator includes: an analog loop filter comprising an outer portion and an inner portion having an input coupled to the outer portion; a quantizer coupled to an output of the inner portion of the analog loop filter; an outer feedback path coupled between an output of the quantizer and an input to the outer portion of the analog loop filter; and a compensation filter coupled between an output of the quantizer and an input of the inner portion of the analog loop filter. The compensation filter has a transfer function configured to correct for an effect of excess loop delay (ELD) on the delta-sigma modulator.
-
-
-
-
-
-
-
-
-
Search Results
88
records
(took 0.032 seconds)
