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    Double-ring network system, method for determining transmission priority in double-ring network and transmission station device
    1.
    发明授权
    Double-ring network system, method for determining transmission priority in double-ring network and transmission station device 有权
    双环网络系统，确定双环网和传输站设备传输优先级的方法

    公开(公告)号：US08724644B2

    公开(公告)日：2014-05-13

    申请号：US13336142

    申请日：2011-12-23

    申请人： Motohiko Okabe ,  Shinya Kohno ,  Koji Shibata

    发明人： Motohiko Okabe ,  Shinya Kohno ,  Koji Shibata

    IPC分类号： H04L12/28

    CPC分类号： H04L12/42 ,  H04L41/12

    摘要： According to one embodiment, in a double-ring network, a master station includes a transmitting and receiving permission switch portion, a communication port A at an A-system side, a communication port B at a B-system side, a first receiving control circuit portion, a transmitting and receiving control circuit portion, a frame detection determining circuit portion, a frame data generating circuit portion, a logical address determining circuit portion, a live list setting circuit portion and an address list setting circuit portion. The master station determines a token order (a transmission priority, also called a logical address) using a shortest path function by the logical address determining circuit portion and the address list setting circuit portion such that the token order does not depend on physical addresses of transmission stations and is matched to a connection order of transmission stations to realize path optimization. This reduces a transmission time.

    摘要翻译： 根据一个实施例，在双环网络中，主站包括发送和接收允许开关部分，A系统侧的通信端口A，B系统侧的通信端口B，第一接收控制 电路部分，发送和接收控制电路部分，帧检测确定电路部分，帧数据产生电路部分，逻辑地址确定电路部分，实况列表设置电路部分和地址列表设置电路部分。 主站通过逻辑地址确定电路部分和地址列表设置电路部分使用最短路径功能来确定令牌顺序（传输优先级，也称为逻辑地址），使得令牌顺序不依赖于传输的物理地址 站与传输站的连接顺序相匹配，实现路径优化。 这减少了传输时间。

    Sharing pipeline by inserting NOP to accommodate memory access request received from other processors
    3.
    发明授权
    Sharing pipeline by inserting NOP to accommodate memory access request received from other processors 有权
    通过插入NOP来共享管道，以适应从其他处理器接收的内存访问请求

    公开(公告)号：US08200950B2

    公开(公告)日：2012-06-12

    申请号：US12478227

    申请日：2009-06-04

    申请人： Motohiko Okabe

    发明人： Motohiko Okabe

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3867 ,  G06F9/3824 ,  G06F9/3836

    摘要： A pipeline operation processor comprises a pipeline processing unit and an instruction insertion controller which inserts an instruction when access to an operation memory is requested, and corrects control information by reference to control information of stages. When a control program is in execution, on receiving an access request instruction requesting for access to the operation memory, the instruction insertion controller inserts an NOP instruction from the instruction decoding unit in place of the access request instruction. The access request instruction is executed while the pipeline processing unit executes no operation, and subsequently, the pipeline processing is continued.

    摘要翻译： 流水线操作处理器包括流水线处理单元和在请求访问操作存储器时插入指令的指令插入控制器，并且通过参考级的控制信息来校正控制信息。 当控制程序执行时，在接收到请求访问操作存储器的访问请求指令时，指令插入控制器从指令解码单元插入NOP指令来代替访问请求指令。 在流水线处理单元不执行操作时执行访问请求指令，随后继续进行流水线处理。

    Light emitting device for transmission of communications information
    4.
    发明授权
    Light emitting device for transmission of communications information 有权
    用于传输通信信息的发光装置

    公开(公告)号：US08053996B2

    公开(公告)日：2011-11-08

    申请号：US12280750

    申请日：2007-02-27

    申请人： Akira Sawada ,  Tetsuya Hara ,  Motohiko Okabe

    发明人： Akira Sawada ,  Tetsuya Hara ,  Motohiko Okabe

    IPC分类号： H05B41/30

    CPC分类号： H05B33/0818 ,  Y02B20/346

    摘要： A light emitting device 1 is adapted, with a distributed power supply voltage, to turn on a light emitter 7, while timing a continuous conduction time with a pulse generating circuit 2, a frequency dividing circuit 3, and a counting memory circuit 4, to flash the light emitter 7 on and off with an on-off pattern depending on a result of the timing, signaling out information on the continuous conduction time.

    摘要翻译： 发光装置1具有分布式电源电压，以使定时与脉冲发生电路2，分频电路3和计数存储电路4的连续导通时间同时接通发光器7， 根据定时结果，使发光器7以开 - 关方式点亮和熄灭，发出关于连续导通时间的信息。

    Light diffusing sheet with direction-dependent diffusing ability
    5.
    发明授权
    Light diffusing sheet with direction-dependent diffusing ability 有权
    具有方向依赖扩散能力的光漫射片

    公开(公告)号：US06606133B1

    公开(公告)日：2003-08-12

    申请号：US09497740

    申请日：2000-02-04

    申请人： Motohiko Okabe

    发明人： Motohiko Okabe

    IPC分类号： G02F11335

    CPC分类号： G02B6/0053 ,  G02B5/0215 ,  G02B5/0231 ,  G02B5/0252 ,  G02B5/0257 ,  G02B5/0268 ,  G02B5/0278

    摘要： A light diffusing sheet capable of changing a backward and forward diffusing ability and a right and left diffusing ability to be adapted to both luminance distribution in a direction perpendicular to a lamp and luminance distribution in the direction parallel to the lamp, and thereby increasing light emanating in a normal direction in either direction and a back light unit using the light diffusing sheet. A light diffusing sheet 1 for use in a back light unit of a liquid crystal display includes light diffusing means which has a backward and forward diffusing ability and a right and left diffusing ability that differ from each other. The light diffusing means includes longitudinally divided spindle shaped convex regions or concave regions formed on a sheet surface, quadrangular pyramid shaped convex regions or concave regions each having a rectangular bottom surface, spindle-shaped light diffusing material dispersed in the sheet with central axes thereof directed in a backward and forward direction or in a right and left direction, and a light diffusing layer in which the spindle-shaped light diffusing materials is dispersed.

    摘要翻译： 一种能够改变向后和向前扩散能力以及左右扩散能力的光漫射片，其适于在与灯垂直的方向上的亮度分布和在与灯平行的方向上的亮度分布，从而增加发光 在任一方向上的法线方向和使用该光漫射片的背光单元。 用于液晶显示器背光单元的光漫射片1包括具有彼此不同的向后和向前扩散能力以及左右扩散能力的光漫射装置。 光扩散装置包括纵向分割的心轴形状的凸起区域或形成在片材表面上的凹陷区域，四边形棱锥形的凸起区域或每个具有矩形底面的凹陷区域，分散在片材中的心轴状光漫射材料，其中心轴线指向 在向前和向前的方向上或在左右方向上，以及漫射层，其中分散有纺锤形的光漫射材料。

    INDUSTRIAL CONTROLLER
    8.
    发明申请
    INDUSTRIAL CONTROLLER 有权
    工业控制器

    公开(公告)号：US20080281896A1

    公开(公告)日：2008-11-13

    申请号：US12108774

    申请日：2008-04-24

    申请人： Yoshito SAMEDA ,  Hiroshi Nakatani ,  Akira Sawada ,  Jun Takehara ,  Hiroyuki Nishikawa ,  Motohiko Okabe

    发明人： Yoshito SAMEDA ,  Hiroshi Nakatani ,  Akira Sawada ,  Jun Takehara ,  Hiroyuki Nishikawa ,  Motohiko Okabe

    IPC分类号： G06F7/48

    CPC分类号： H04L9/008 ,  G06F11/085

    摘要： A first arithmetic operator (11) includes a first modular arithmetic coding encoder (11b) for encoding a numeric data transmitted by a command from a central controller (31) into a modular arithmetic code, a first arithmetic operation processor (11a) using the numeric data as modular arithmetic coded as an input operand, for executing an arithmetic operation based on a command from the central controller (13), to provide an output in the form of a modular arithmetic code, and a first modular arithmetic code decoder (11c) for determining presence or absence of a bit error in the numeric data output from the first arithmetic operation processor, correcting the bit error, if detected any, to output a decoded numeric data.

    摘要翻译： 第一算术运算器（11）包括：第一模数算术编码编码器（11b），用于将通过中央控制器（31）的命令发送的数值数据编码为模数运算代码;第一算术运算处理器（11a），使用 将作为输入操作数编码的模数算术的数值数据作为基于来自中央控制器（13）的命令执行算术运算，提供模数运算代码形式的输出和第一模运算代码解码器（ 11c）用于确定从第一算术运算处理器输出的数值数据中存在或不存在位错误，如果检测到的话，校正位错误，以输出解码的数字数据。

    Redundancy control system and method of transmitting computational data thereof for detection of transmission errors and failure diagnosis
    9.
    发明授权
    Redundancy control system and method of transmitting computational data thereof for detection of transmission errors and failure diagnosis 有权
    冗余控制系统及其发送计算数据的方法，用于检测传输错误和故障诊断

    公开(公告)号：US08762788B2

    公开(公告)日：2014-06-24

    申请号：US13206898

    申请日：2011-08-10

    申请人： Hiroshi Nakatani ,  Naoya Ohnishi ,  Makoto Toko ,  Motohiko Okabe

    发明人： Hiroshi Nakatani ,  Naoya Ohnishi ,  Makoto Toko ,  Motohiko Okabe

    IPC分类号： G06F11/14

    CPC分类号： G05B9/03 ,  G05B19/0428 ,  G05B2219/24187

    摘要： A redundancy control system and method of transmitting computational data are provided, for detection of transmission errors and failure diagnosis, including generating first computational data and generating first generated data using a first generation algorithm for error detection; generating second computational data and generating second generated data using a second generation algorithm for error detection; comparing the first/second computational data; transmitting transmission data including coincident computational data and the first/second generated data; generating, in the receiving device, computational data and third/fourth generated data from preset first/second generation algorithms; and comparing the first/third generated data and the first/third generated data, and detecting the presence or absence of an error in the received computational data.

    摘要翻译： 提供了一种发送计算数据的冗余控制系统和方法，用于检测传输错误和故障诊断，包括生成第一计算数据，并使用第一代算法生成第一生成数据进行错误检测; 产生第二计算数据并使用用于错误检测的第二代算法产生第二生成数据; 比较第一/第二计算数据; 发送包括一致的计算数据和所述第一/第二生成数据的传输数据; 在接收装置中从预设的第一/第二代算法生成计算数据和第三/第四生成数据; 以及比较所述第一/第三生成数据和所述第一/第三生成数据，并且检测所接收的计算数据中是否存在错误。

    Bus signal control circuit for detecting bus signal abnormalities using separate bus diagnosis line
    10.
    发明授权
    Bus signal control circuit for detecting bus signal abnormalities using separate bus diagnosis line 有权
    总线信号控制电路，用于使用单独的总线诊断线检测总线信号异常

    公开(公告)号：US08131900B2

    公开(公告)日：2012-03-06

    申请号：US12432896

    申请日：2009-04-30

    申请人： Jun Takehara ,  Naruhiko Aramaki ,  Toshikazu Kawamura ,  Yoshito Sameda ,  Hiroshi Nakatani ,  Motohiko Okabe ,  Yukitaka Yoshida

    发明人： Jun Takehara ,  Naruhiko Aramaki ,  Toshikazu Kawamura ,  Yoshito Sameda ,  Hiroshi Nakatani ,  Motohiko Okabe ,  Yukitaka Yoshida

    IPC分类号： G06F13/00 ,  H04L1/14

    CPC分类号： G06F11/0793 ,  G06F11/0745

    摘要： A memory control unit controls writing and reading of data to the slave device according to an instruction from the master device. A bus diagnosis line is directly connected from the bus signal control circuit to a bus signal receiving terminal of the slave device without passing through the address bus and the control signal line. A bus signal abnormality processing unit compares an output bus signal output from the bus signal control circuit to the address bus and the control signal line with a feedback bus signal fed back through the bus diagnosis line to determine the presence/absence of a difference. The memory control unit elongates a bus cycle period of a bus cycle of operation being executed when it is determined in the bus signal abnormality processing unit that the difference is present.

    摘要翻译： 存储器控制单元根据来自主设备的指令控制对从设备的数据的写入和读取。 总线诊断线从总线信号控制电路直接连接到从设备的总线信号接收终端，而不通过地址总线和控制信号线。 总线信号异常处理单元将从总线信号控制电路输出的输出总线信号与地址总线和控制信号线进行比较，其中反馈总线信号通过总线诊断线反馈，以确定差异的存在/不存在。 当在总线信号异常处理单元中确定存在差异时，存储器控制单元延长正在执行的总线周期的总线周期。