公开(公告)号：US4924290A

公开(公告)日：1990-05-08

申请号：US238122

申请日：1988-08-30

申请人： Motohiro Enkaku ,  Toshiya Kato

发明人： Motohiro Enkaku ,  Toshiya Kato

IPC分类号： H01L21/82 ,  H01L21/822 ,  H01L23/528 ,  H01L23/538 ,  H01L27/04 ,  H01L27/118

CPC分类号： H01L23/5384 ,  H01L23/528 ,  H01L23/5286 ,  H01L24/06 ,  H01L2924/14

摘要： A semiconductor device includes a circuit block formed on a semiconductor chip with multilayered wiring layers having two or more layers, and having a specific function assigned thereto, a first current path pattern formed in a first layer of the multilayered wiring layers and running around the circuit block, a second current path pattern formed in a second layer of the multilayered wiring layers and running around the circuit block, part of the second current path pattern lying over the first current path pattern and the other portion of the second current path pattern lying off the first current path pattern so as to define a connection space with a predetermined width between the first current path pattern and the second current path pattern, a first signal path pattern formed in the first layer of the multilayered wiring layers and serving as a signal path to the circuit block, a second signal path pattern formed in the second layer of the multilayered wiring layers and serving as the signal path to the circuit block, and a via contact, formed in the connection space, for electrically coupling the first signal path pattern and the second signal path pattern.

公开(公告)号：US4970572A

公开(公告)日：1990-11-13

申请号：US318791

申请日：1989-03-03

申请人： Toshiya Kato ,  Motohiro Enkaku

发明人： Toshiya Kato ,  Motohiro Enkaku

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L23/5286 ,  H01L23/5226 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2924/14

摘要： A semiconductor integrated circuit device of multi-layer interconnection structure includes a pad formed of a multilayer interconnection layer. The power source pad is connected to a power source interconnection layer via a lead-out interconnection layer which is formed of the same multilayer interconnection layer as that used to form the power source pad.

公开(公告)号：US07334174B2

公开(公告)日：2008-02-19

申请号：US10806244

申请日：2004-03-23

申请人： Motohiro Enkaku

发明人： Motohiro Enkaku

IPC分类号： G01R31/28

CPC分类号： G11C17/18

摘要： A semiconductor integrated circuit device includes a programmable circuit in which information is programmed, an information holding circuit which electrically holds information programmed in the programmable circuit, a compression circuit which compresses information held in the information holding circuit, an information output circuit which outputs expected value information, and a detection circuit which checks whether information held in the information holding circuit is destroyed or not. The detecting circuit compares expected value information of the information output circuit with compression information of the information compression circuit to check destruction of information held in the information holding circuit.

摘要翻译： 一种半导体集成电路装置，其中包括编程信息的可编程电路，用于电气地保存可编程电路中编程的信息的信息保持电路，压缩信息保持电路中保存的信息的压缩电路，输出期望值的信息输出电路 信息和检测信息保持电路中保存的信息是否被破坏的检测电路。 检测电路将信息输出电路的预期值信息与信息压缩电路的压缩信息进行比较，以检查信息保持电路中保存的信息的破坏。

公开(公告)号：US20050050421A1

公开(公告)日：2005-03-03

申请号：US10806244

申请日：2004-03-23

申请人： Motohiro Enkaku

发明人： Motohiro Enkaku

IPC分类号： G01R31/28 ,  G06F11/00 ,  G06F12/16 ,  G11C7/00 ,  G11C17/18 ,  G11C29/00 ,  G11C29/04

CPC分类号： G11C17/18

摘要： A semiconductor integrated circuit device includes a programmable circuit in which information is programmed, an information holding circuit which electrically holds information programmed in the programmable circuit, a compression circuit which compresses information held in the information holding circuit, an information output circuit which outputs expected value information, and a detection circuit which checks whether information held in the information holding circuit is destroyed or not. The detecting circuit compares expected value information of the information output circuit with compression information of the information compression circuit to check destruction of information held in the information holding circuit.

摘要翻译： 一种半导体集成电路装置，其中包括编程信息的可编程电路，用于电气地保存可编程电路中编程的信息的信息保持电路，压缩信息保持电路中保存的信息的压缩电路，输出期望值的信息输出电路 信息和检测信息保持电路中保存的信息是否被破坏的检测电路。 检测电路将信息输出电路的预期值信息与信息压缩电路的压缩信息进行比较，以检查信息保持电路中保存的信息的破坏。

公开(公告)号：US5952850A

公开(公告)日：1999-09-14

申请号：US937123

申请日：1997-09-24

申请人： Takehiko Hojo ,  Motohiro Enkaku

发明人： Takehiko Hojo ,  Motohiro Enkaku

IPC分类号： H03K19/0175 ,  H03K19/00 ,  H03K19/094

CPC分类号： H03K19/0013

摘要： An I/O circuit is capable of achieving a reduction of power consumption by preventing leak current while performing the pull-down or pull-up operation. The I/O circuit of the present invention is constructed so that an I/O terminal 5 is pulled down or pulled up only when the I/O terminal 5 is in an open state or at the same potential as the pull-down or pull-up potential provided to the I/O terminal 5 when the high impedance state is input to the I/O terminal 5. The I/O circuit comprises an output circuit providing tri-state outputs, a switch circuit for the pull-up or pull-down operation, and an input circuit connected to the I/O terminal, the switch circuit and internal circuits of a device.

摘要翻译： I / O电路能够通过在执行下拉或上拉操作时防止泄漏电流来实现功耗的降低。 本发明的I / O电路被构造成仅当I / O端子5处于打开状态或与下拉或拉动相同的电位时I / O端子5被拉下或拉起 当高阻抗状态被输入到I / O端子5时，提供给I / O端子5的电位.I / O电路包括提供三态输出的输出电路，用于上拉的开关电路或 下拉操作以及连接到I / O端子，开关电路和器件的内部电路的输入电路。

公开(公告)号：US5929469A

公开(公告)日：1999-07-27

申请号：US992542

申请日：1997-12-17

申请人： Kenichiro Mimoto ,  Motohiro Enkaku ,  Takehiko Hojo

发明人： Kenichiro Mimoto ,  Motohiro Enkaku ,  Takehiko Hojo

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L21/82 ,  H01L21/8234 ,  H01L23/52 ,  H01L27/088 ,  H01L27/118

CPC分类号： H01L27/11807 ,  H01L2924/0002

摘要： In a first inter-layer insulator film above source/drain regions of basic cells constituting a gate array, first contact holes (joint contacts) are placed, so that wings (joint plates) electrically connected with the source/drain regions via plugs in those joint contacts is locally placed above the source/drain regions. Above the wings is formed a second inter-layer insulator film, above which is formed a first level interconnection which constitutes one of metal wiring layers. In the second inter-layer insulator film are formed second contact holes, so that a semi-custom ASIC is provided in which the wings and the first level interconnection are electrically interconnected via the plugs in those second contact holes. The first and second contact holes, first level interconnection, etc. are automatically designed by use of a computer based on a grid pattern in the basic cells. According to the present invention, the basic cells need not be re-designed even if a first pitch of a pattern of the first contact holes is different from a second pitch of a pattern of the second contact holes, thus easily enabling automatic customization. Without increasing the area of the source/drain regions in the basic cells, any pitch of the wiring layers can be selected, thus increasing the integration density without deteriorating the performance of MOS FETs at the same time as reducing time required for the customization.

摘要翻译： 在构成门阵列的基本单元的源极/漏极区域上方的第一层间绝缘膜中，放置第一接触孔（接合触点），使得通过插头在源极/漏极区域中电连接的翼（接合板） 接头接点局部放置在源极/漏极区域之上。 翼上方形成有第二层间绝缘膜，其上形成有构成金属布线层之一的第一层互连。 在第二层间绝缘体膜中形成第二接触孔，从而提供半定制ASIC，其中翼和第一级互连通过那些第二接触孔中的插塞电互连。 通过使用基于基本单元格中的网格图案的计算机来自动设计第一和第二接触孔，第一层互连等。 根据本发明，即使第一接触孔的图案的第一间距与第二接触孔的图案的第二间距不同，基本单元也不需要重新设计，因此容易实现自动定制。 在不增加基本单元中的源极/漏极区域的面积的情况下，可以选择布线层的任何间距，从而在降低定制所需时间的同时增加集成密度，而不会降低MOS FET的性能。