公开(公告)号：US06553477B1

公开(公告)日：2003-04-22

申请号：US09707347

申请日：2000-11-06

申请人： Murali V. Krishna ,  Vipul Parikh ,  Michael Butler ,  Gene Shen ,  Masahito Kubo

发明人： Murali V. Krishna ,  Vipul Parikh ,  Michael Butler ,  Gene Shen ,  Masahito Kubo

IPC分类号： G06F1200

CPC分类号： G06F12/126 ,  G06F12/1027 ,  G06F2212/681

摘要： A microprocessor is equipped with an address translation mechanism for performing dynamic address translation from a virtual address to a physical address on a page-by-page basis. The microprocessor includes a large-capacity low-associativity address translation buffer, and is capable of avoiding limitations imposed on a TLB entry lock function, while reducing the overhead for address translation. The address translation mechanism comprises an address translation buffer having an entry lock function, and control logic for controlling the operation of the address translation buffer. The address translation buffer includes a lower-level buffer organized as a lower-level hierarchy of the address translation buffer and having no entry lock function, and a higher-level buffer organized as a higher-level hierarchy of the address translation buffer and having an entry lock function, the higher-level buffer having higher associativity than the associativity of the lower-level buffer.

摘要翻译： 微处理器配备有地址转换机制，用于逐页地执行从虚拟地址到物理地址的动态地址转换。 微处理器包括大容量低关联地址转换缓冲器，并能够避免对TLB条目锁定功能的限制，同时减少地址转换的开销。 地址转换机构包括具有条目锁定功能的地址转换缓冲器和用于控制地址转换缓冲器的操作的控制逻辑。 地址转换缓冲器包括被组织为地址转换缓冲器的较低层级并且不具有条目锁定功能的下级缓冲器，以及组织为地址转换缓冲器的更高级别层级的较高级缓冲器，并且具有 入口锁定功能，高级缓冲器具有比下级缓冲器的关联性更高的关联性。

公开(公告)号：US06832326B2

公开(公告)日：2004-12-14

申请号：US09808343

申请日：2001-03-15

申请人： Masahito Kubo ,  Haruhiko Ueno ,  Akikazu Nakagawa

发明人： Masahito Kubo ,  Haruhiko Ueno ,  Akikazu Nakagawa

IPC分类号： G06F112

CPC分类号： G06F1/14

摘要： In a multi-processor system, each processor transmits a system time synchronous signal to another processor using hardware, and measures the propagation delay time of the signal. Then, the timer value of each processor is adjusted with the measured propagation delay time.

摘要翻译： 在多处理器系统中，每个处理器使用硬件向另一个处理器发送系统时间同步信号，并测量信号的传播延迟时间。 然后，用测量的传播延迟时间调整每个处理器的定时器值。

公开(公告)号：US07337347B2

公开(公告)日：2008-02-26

申请号：US10998151

申请日：2004-11-29

申请人： Masahito Kubo ,  Takashi Chiba ,  Masakazu Takahashi ,  Shinichiro Nakamura ,  Kenji Takebe ,  Hirofumi Koseki

发明人： Masahito Kubo ,  Takashi Chiba ,  Masakazu Takahashi ,  Shinichiro Nakamura ,  Kenji Takebe ,  Hirofumi Koseki

IPC分类号： G06F1/04 ,  G06F1/00 ,  G06F1/12 ,  G06F5/06

CPC分类号： G06F1/14

摘要： An elapsed cycle number during the predetermined period of the inputted clock source is counted using the clock reference signal as a yardstick, a frequency of the clock source is computed based on an elapsed cycle number obtained by counting, control timing of various interfaces relating to the CPU is adjusted and an interruption generating interval in which interruption is generated regularly by the CPU so that adjustment of control timing of various interfaces and setting of a timer interruption interval during the OS operation in accordance with a frequency of the clock source without performing OS modification such as rebuilding and the like.

摘要翻译： 使用时钟参考信号作为衡量标准，在输入的时钟源的预定时段期间的经过周期数被计数，基于通过计数获得的经过的周期数来计算时钟源的频率，控制与 CPU被调整，并且中断生成间隔由CPU定期产生中断，从而根据时钟源的频率在OS操作期间调整各种接口的控制定时并设置定时器中断间隔，而不进行OS修改 例如重建等。

公开(公告)号：US20050240830A1

公开(公告)日：2005-10-27

申请号：US10998152

申请日：2004-11-29

申请人： Masahito Kubo ,  Takashi Chiba ,  Hirofumi Koseki

发明人： Masahito Kubo ,  Takashi Chiba ,  Hirofumi Koseki

IPC分类号： G06F11/30 ,  G06F11/00 ,  G06F11/34 ,  G06F13/00

CPC分类号： G06F11/006 ,  G06F11/0724 ,  G06F11/0778

摘要： In the initialization of a multiprocessor system, device history information containing mounting position information indicating a mounting position of a CPU board supplied from a history information supplying unit is stored in a nonvolatile storage unit in the CPU board capable of storing plural pieces of device history information, so that the mounting position information on each of CPU boards can be accurately and automatically recorded in each CPU board and the history of the mounting position of the CPU board can be recorded and managed on a CPU board by CPU board basis.

摘要翻译： 在多处理器系统的初始化中，包含表示从历史信息提供单元提供的CPU板的安装位置的安装位置信息的设备历史信息被存储在能够存储多条设备历史信息的CPU板中的非易失性存储单元中 ，因此能够将各CPU板上的安装位置信息准确自动地记录在CPU板上，并且可以通过CPU板对CPU板的安装位置的历史进行记录和管理。

公开(公告)号：US4788655A

公开(公告)日：1988-11-29

申请号：US874700

申请日：1986-06-16

申请人： Yozo Nakayama ,  Masahito Kubo ,  Yuuichi Yawata

发明人： Yozo Nakayama ,  Masahito Kubo ,  Yuuichi Yawata

IPC分类号： G06F7/00 ,  G06F7/38 ,  G06F7/483 ,  G06F7/57 ,  G06F9/22 ,  G06F9/32

CPC分类号： G06F7/57 ,  G06F9/226 ,  G06F9/30094 ,  G06F7/49905

摘要： A condition code producing system for an arithmetic unit which is controlled by a micro program and operate on binary floating point data produces a condition code having a plurality of bits and describing an attribute of the binary floating point data. The condition code producing system comprises: a storing device for storing each bit of the condition code; a device for producing a plurality of detection signals from values of predetermined bits of the binary floating point data. This data is transferred to a bus within the arithmetic unit by a micro instruction which involves a data transfer, where the micro instruction is one of a plurality of micro instructions constituting the micro program. The micro instruction comprises a condition control field constituted by a plurality of bits having values depending on at least precision and data portions of the binary floating point data which is transferred. The system also includes a device for producing a new condition code from the plurality of detection signals and the condition code already stored in the storing device depending on a value of the condition control field and for setting the new condition code in the storing device.

摘要翻译： 用于由微程序控制并对二进制浮点数据进行操作的运算单元的条件代码产生系统产生具有多个位的条件码并描述二进制浮点数据的属性。 条件码产生系统包括：存储装置，用于存储条件码的每一位; 用于根据二进制浮点数据的预定位的值产生多个检测信号的装置。 该数据通过涉及数据传送的微指令传送到算术单元内的总线，其中微指令是构成微程序的多个微指令之一。 微指令包括由多个比特构成的条件控制字段，该多个比特具有取决于至少精度的值和被传送的二进制浮点数据的数据部分。 该系统还包括根据条件控制字段的值从已经存储在存储装置中的多个检测信号和条件代码产生新的条件代码的装置，并且用于在存储装置中设置新的条件代码。

公开(公告)号：US20050268143A1

公开(公告)日：2005-12-01

申请号：US10998151

申请日：2004-11-29

申请人： Masahito Kubo ,  Takashi Chiba ,  Masakazu Takahashi ,  Shinichiro Nakamura ,  Kenji Takebe ,  Hirofumi Koseki

发明人： Masahito Kubo ,  Takashi Chiba ,  Masakazu Takahashi ,  Shinichiro Nakamura ,  Kenji Takebe ,  Hirofumi Koseki

IPC分类号： G06F9/30 ,  G06F1/04 ,  G06F1/08 ,  G06F1/14 ,  G06F1/24

CPC分类号： G06F1/14

摘要： An elapsed cycle number during the predetermined period of the inputted clock source is counted using the clock reference signal as a yardstick, a frequency of the clock source is computed based on an elapsed cycle number obtained by counting, control timing of various interfaces relating to the CPU is adjusted and an interruption generating interval in which interruption is generated regularly by the CPU so that adjustment of control timing of various interfaces and setting of a timer interruption interval during the OS operation in accordance with a frequency of the clock source without performing OS modification such as rebuilding and the like.

摘要翻译： 使用时钟参考信号作为衡量标准，在输入的时钟源的预定时段期间的经过周期数被计数，基于通过计数获得的经过的周期数来计算时钟源的频率，控制与 CPU被调整，并且中断生成间隔由CPU定期产生中断，从而根据时钟源的频率在OS操作期间调整各种接口的控制定时并设置定时器中断间隔，而不进行OS修改 例如重建等。