公开(公告)号：US20230099467A1

公开(公告)日：2023-03-30

申请号：US17947446

申请日：2022-09-19

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Takumi ENDOU ,  Sho WATANABE ,  Akito MORI ,  Masahiro WAKASHIMA

IPC: H01G4/12 ,  H01G4/008

Abstract: A multilayer ceramic capacitor includes dielectric layers made of a ceramic material and internal electrode layers laminated therein. The internal electrode layers each include dielectric columns provided therein. A solid solution layer in which S is solidly dissolved is provided at an interface between each of the dielectric columns and each of the internal electrode layers.

公开(公告)号：US20220102079A1

公开(公告)日：2022-03-31

申请号：US17487385

申请日：2021-09-28

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Keita KITAHARA ,  Yuta SAITO ,  Noriyuki OOKAWA ,  Riyousuke AKAZAWA ,  Takefumi TAKAHASHI ,  Masahiro WAKASHIMA ,  Yuta KUROSU ,  Akito MORI

IPC: H01G4/30 ,  H01G4/008 ,  H01G4/12 ,  H01G4/012

Abstract: A multilayer ceramic capacitor includes a multilayer body including dielectric layers and internal electrode layers alternately laminated therein, and external electrode layers respectively provided on both end surfaces of the multilayer body in a length direction intersecting a lamination direction, and each connected to the internal electrode layers, the external electrode layers each further including a base electrode layer including a first region, a second region, and a third region divided therein, in order from the multilayer body. The first region includes a metal included in the internal electrode layers in a higher amount than the second region and the third region, the second region includes glass in a higher amount than the first region and the third region, and the third region includes copper in a higher amount than the first region and the second region.

公开(公告)号：US20250037939A1

公开(公告)日：2025-01-30

申请号：US18913062

申请日：2024-10-11

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Akito MORI ,  Masahiro WAKASHIMA ,  Sho WATANABE ,  Takumi ENDOU

IPC: H01G4/30 ,  H01G4/008 ,  H01G4/12

Abstract: A multilayer ceramic capacitor includes a multilayer body including an inner layer portion including internal electrode layers and inner dielectric layers laminated alternately, and internal electrode layers at both ends thereof in a lamination direction, and outer dielectric layers covering the inner layer portion, and two external electrodes on both end surfaces of the multilayer body in a length direction intersecting the lamination direction. The inner and outer dielectric layers each include grains, and a difference between an average grain size of grains in the inner dielectric layers and an average grain size of grains in the outer dielectric layers is about 100 nm or less.

公开(公告)号：US20230352243A1

公开(公告)日：2023-11-02

申请号：US18218300

申请日：2023-07-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Keita KITAHARA ,  Yuta SAITO ,  Noriyuki OOKAWA ,  Riyousuke AKAZAWA ,  Takefumi TAKAHASHI ,  Masahiro WAKASHIMA ,  Yuta KUROSU ,  Akito MORI

IPC: H01G4/30 ,  H01G4/008 ,  H01G4/12 ,  H01G4/012

CPC classification number: H01G4/30 ,  H01G4/008 ,  H01G4/1218 ,  H01G4/012

Abstract: In a multilayer ceramic capacitor, a positional deviation in a lamination direction between end portions in a width direction intersecting the lamination direction and a length direction, of two of internal electrode layers adjacent to each other in the lamination direction, is about 5 μm or less. A connection ratio N1/N0 at the middle portion thereof, and a connection ratio N2/N0 at the end portion thereof are about 90% or more, respectively, and a difference between N1/N0 and N2/N0 is about 10% or less.

公开(公告)号：US20220102077A1

公开(公告)日：2022-03-31

申请号：US17487349

申请日：2021-09-28

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Keita KITAHARA ,  Yuta SAITO ,  Noriyuki OOKAWA ,  Riyousuke AKAZAWA ,  Takefumi TAKAHASHI ,  Masahiro WAKASHIMA ,  Yuta KUROSU ,  Akito MORI

IPC: H01G4/30 ,  H01G4/012 ,  H01G4/12 ,  H01G4/008

Abstract: In a multilayer ceramic capacitor, a positional deviation in a lamination direction between end portions in a width direction intersecting the lamination direction and a length direction, of two of internal electrode layers adjacent to each other in the lamination direction, is about 5 μm or less. A connection ratio N1/N0 at the middle portion thereof, and a connection ratio N2/N0 at the end portion thereof are about 90% or more, respectively, and a difference between N1/N0 and N2/N0 is about 10% or less.

公开(公告)号：US20240105391A1

公开(公告)日：2024-03-28

申请号：US18524673

申请日：2023-11-30

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Keita KITAHARA ,  Yuta SAITO ,  Noriyuki OOKAWA ,  Riyousuke AKAZAWA ,  Takefumi TAKAHASHI ,  Masahiro WAKASHIMA ,  Yuta KUROSU ,  Akito MORI

IPC: H01G4/232 ,  H01G4/008 ,  H01G4/12 ,  H01G4/30

CPC classification number: H01G4/2325 ,  H01G4/008 ,  H01G4/1227 ,  H01G4/30

Abstract: A multilayer ceramic capacitor includes a multilayer body including dielectric layers and internal electrode layers alternately laminated therein, base electrode layers respectively provided on both end surfaces of the multilayer body in a length direction intersecting a lamination direction, and each connected to the internal electrode layers and each including glass and copper, and plated layers respectively provided on an outer side of the base electrode layers. A protective layer including sulfur is provided between the glass included in the base electrode layers and the plated layers.

公开(公告)号：US20230317374A1

公开(公告)日：2023-10-05

申请号：US18109309

申请日：2023-02-14

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Natsuko OKUBO ,  Akito MORI ,  Kazuhisa UCHIDA

IPC: H01G4/12 ,  H01G4/30 ,  H01G4/008 ,  H01G4/012

CPC classification number: H01G4/1227 ,  H01G4/008 ,  H01G4/012 ,  H01G4/30 ,  H01G4/1236

Abstract: A multilayer ceramic capacitor includes a multilayer body including dielectric layers and internal electrode layers, and external electrodes. The multilayer body includes side margin portions made of a dielectric. In the internal electrode layers, a width of an extension electrode portion is smaller than a width of a counter electrode portion. The side margin portions each include Ba and Ti as a main component and Mg as a sub component. The Mg content is about 0.2 mol% or more and about 2.0 mol% or less with respect to 100 mol of Ti. The internal electrode layers each include Ni as a main component, and an end portion of the counter electrode portion includes Mg as a sub component. The Mg content is about 0.13 mol% or more and about 0.39 mol% or less with respect to 100 mol of Ni.

公开(公告)号：US20230101251A1

公开(公告)日：2023-03-30

申请号：US17947271

申请日：2022-09-19

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Akito MORI ,  Masahiro WAKASHIMA ,  Sho WATANABE ,  Takumi ENDOU

IPC: H01G4/30 ,  H01G4/12 ,  H01G4/008

Abstract: A multilayer ceramic capacitor includes a multilayer body including an inner layer portion including internal electrode layers and inner dielectric layers laminated alternately, and internal electrode layers at both ends thereof in a lamination direction, and outer dielectric layers covering the inner layer portion, and two external electrodes on both end surfaces of the multilayer body in a length direction intersecting the lamination direction. The inner and outer dielectric layers each include grains, and a difference between an average grain size of grains in the inner dielectric layers and an average grain size of grains in the outer dielectric layers is about 100 nm or less.

公开(公告)号：US20210098191A1

公开(公告)日：2021-04-01

申请号：US16988754

申请日：2020-08-10

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yuta SAITO ,  Akito MORI ,  Takefumi TAKAHASHI ,  Masahiro WAKASHIMA

IPC: H01G4/232 ,  H01G4/30 ,  H01G4/12 ,  H01G4/008

Abstract: A multilayer ceramic capacitor includes a laminate including dielectric layers and internal electrode layers laminated together in a lamination direction, and a pair of external electrodes on both end surfaces of the laminate, the external electrodes being connected to the internal electrode layers, wherein a barrier is provided on a widthwise end of at least one internal electrode layer, the barrier having a thickness that decreases from the widthwise end of the internal electrode layer toward a side margin in a width direction, a void is defined by the widthwise end of the internal electrode layer, the barrier, and the side margin, and the barrier contains Ni and Sn.

公开(公告)号：US20200312555A1

公开(公告)日：2020-10-01

申请号：US16822068

申请日：2020-03-18

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Akitaka DOI ,  Akito MORI ,  Kazuhisa UCHIDA

IPC: H01G4/12 ,  H01G4/012 ,  H01G4/232

Abstract: A multilayer ceramic capacitor includes a laminate including a dielectric ceramic layer and first and second electrode layers laminated in a lamination direction, and first and second external electrodes respectively connected to the first and second internal electrode layers. The laminate includes a central layer portion, a peripheral layer portion sandwiching the central layer portion, and a side margin sandwiching the central layer portion and the peripheral layer portion. The first and second internal electrode layers and the first and second external electrodes include Ni. In a cross section including the lamination direction and a width direction, a Ni content of the peripheral layer portion is larger at a surface portion than at a central portion in a thickness direction, and a Ni content of the side margin is larger at a surface portion than at a central portion in a thickness direction of the side margin.