公开(公告)号：US20230352243A1

公开(公告)日：2023-11-02

申请号：US18218300

申请日：2023-07-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Keita KITAHARA ,  Yuta SAITO ,  Noriyuki OOKAWA ,  Riyousuke AKAZAWA ,  Takefumi TAKAHASHI ,  Masahiro WAKASHIMA ,  Yuta KUROSU ,  Akito MORI

IPC: H01G4/30 ,  H01G4/008 ,  H01G4/12 ,  H01G4/012

CPC classification number: H01G4/30 ,  H01G4/008 ,  H01G4/1218 ,  H01G4/012

Abstract: In a multilayer ceramic capacitor, a positional deviation in a lamination direction between end portions in a width direction intersecting the lamination direction and a length direction, of two of internal electrode layers adjacent to each other in the lamination direction, is about 5 μm or less. A connection ratio N1/N0 at the middle portion thereof, and a connection ratio N2/N0 at the end portion thereof are about 90% or more, respectively, and a difference between N1/N0 and N2/N0 is about 10% or less.

公开(公告)号：US20220102077A1

公开(公告)日：2022-03-31

申请号：US17487349

申请日：2021-09-28

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Keita KITAHARA ,  Yuta SAITO ,  Noriyuki OOKAWA ,  Riyousuke AKAZAWA ,  Takefumi TAKAHASHI ,  Masahiro WAKASHIMA ,  Yuta KUROSU ,  Akito MORI

IPC: H01G4/30 ,  H01G4/012 ,  H01G4/12 ,  H01G4/008

Abstract: In a multilayer ceramic capacitor, a positional deviation in a lamination direction between end portions in a width direction intersecting the lamination direction and a length direction, of two of internal electrode layers adjacent to each other in the lamination direction, is about 5 μm or less. A connection ratio N1/N0 at the middle portion thereof, and a connection ratio N2/N0 at the end portion thereof are about 90% or more, respectively, and a difference between N1/N0 and N2/N0 is about 10% or less.

公开(公告)号：US20210327645A1

公开(公告)日：2021-10-21

申请号：US17203855

申请日：2021-03-17

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Takefumi TAKAHASHI

IPC: H01G4/232 ,  H01G4/30 ,  H01G4/248 ,  H01G4/12

Abstract: A multilayer ceramic electronic component includes a multilayer body, and an external electrode layer including a foundation electrode layer which is a fired layer. The multilayer body includes an inner layer portion including ceramic layers and inner conductive layers, and outer layer portions each including the ceramic layers. The foundation electrode layer includes an inner layer electrode portion adjacent to the inner layer portion and outer layer electrode portions respectively adjacent to the outer layer portions. The outer layer electrode portions respectively include high-content regions and low-content regions in order from an end surface of the multilayer body. The content of metal in the high-content regions is higher than the content of metal in the low-content regions.

公开(公告)号：US20230197346A1

公开(公告)日：2023-06-22

申请号：US18081745

申请日：2022-12-15

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Keita KITAHARA ,  Riyousuke AKAZAWA ,  Takefumi TAKAHASHI

IPC: H01G4/232 ,  H01G4/30

CPC classification number: H01G4/2325 ,  H01G4/30

Abstract: A multilayer ceramic capacitor includes a multilayer body including internal electrode layers and internal dielectric layers alternatively laminated, main surfaces on both sides in a lamination direction, end surfaces on both sides in a length direction intersecting the lamination direction, and lateral surfaces on both sides in a width direction intersecting the lamination direction and the length direction, and external electrodes on the end surfaces of the multilayer body. The external electrodes each include a base electrode layer including a Cu region including Cu as a main component and at least one glass region including Si as a main component, and a plated layer covering the base electrode layer. On a surface of the base electrode layer covered by the plated layer, at least one glass region protrudes from the Cu region.

公开(公告)号：US20220102079A1

公开(公告)日：2022-03-31

申请号：US17487385

申请日：2021-09-28

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Keita KITAHARA ,  Yuta SAITO ,  Noriyuki OOKAWA ,  Riyousuke AKAZAWA ,  Takefumi TAKAHASHI ,  Masahiro WAKASHIMA ,  Yuta KUROSU ,  Akito MORI

IPC: H01G4/30 ,  H01G4/008 ,  H01G4/12 ,  H01G4/012

Abstract: A multilayer ceramic capacitor includes a multilayer body including dielectric layers and internal electrode layers alternately laminated therein, and external electrode layers respectively provided on both end surfaces of the multilayer body in a length direction intersecting a lamination direction, and each connected to the internal electrode layers, the external electrode layers each further including a base electrode layer including a first region, a second region, and a third region divided therein, in order from the multilayer body. The first region includes a metal included in the internal electrode layers in a higher amount than the second region and the third region, the second region includes glass in a higher amount than the first region and the third region, and the third region includes copper in a higher amount than the first region and the second region.

公开(公告)号：US20240290546A1

公开(公告)日：2024-08-29

申请号：US18657890

申请日：2024-05-08

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Keita KITAHARA ,  Yuta SAITO ,  Noriyuki OOKAWA ,  Riyousuke AKAZAWA ,  Takefumi TAKAHASHI ,  Masahiro WAKASHIMA ,  Yuta KUROSU ,  Akito MORI

IPC: H01G4/30 ,  H01G4/008 ,  H01G4/012 ,  H01G4/12

CPC classification number: H01G4/30 ,  H01G4/008 ,  H01G4/012 ,  H01G4/1218

Abstract: In a multilayer ceramic capacitor, a positional deviation in a lamination direction between end portions in a width direction intersecting the lamination direction and a length direction, of two of internal electrode layers adjacent to each other in the lamination direction, is about 5 μm or less. A connection ratio N1/N0 at the middle portion thereof, and a connection ratio N2/N0 at the end portion thereof are about 90% or more, respectively, and a difference between N1/N0 and N2/N0 is about 10% or less.

公开(公告)号：US20240029958A1

公开(公告)日：2024-01-25

申请号：US18375681

申请日：2023-10-02

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Keita KITAHARA ,  Yuta SAITO ,  Noriyuki OOKAWA ,  Riyousuke AKAZAWA ,  Takefumi TAKAHASHI ,  Masahiro WAKASHIMA ,  Yuta KUROSU ,  Akito MORI

IPC: H01G4/30 ,  H01G4/12 ,  H01G4/008 ,  H01G4/012

CPC classification number: H01G4/30 ,  H01G4/1218 ,  H01G4/008 ,  H01G4/012

Abstract: A multilayer ceramic capacitor includes a multilayer body including an inner layer portion including dielectric layers and internal electrode layers alternately laminated therein, two outer layer portions respectively provided on both sides of the inner layer portion in a lamination direction, and two side gap portions respectively provided on both side surfaces of the inner layer portion and the outer layer portions, in a width direction intersecting the lamination direction, and external electrodes respectively provided on both end surfaces of the multilayer body in a length direction intersecting the lamination direction and the width direction, and each connected to the internal electrode layers, wherein nickel and magnesium are segregated between the side gap portions and the outer layer portions.

公开(公告)号：US20230360856A1

公开(公告)日：2023-11-09

申请号：US18218303

申请日：2023-07-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Keita KITAHARA ,  Yuta SAITO ,  Noriyuki OOKAWA ,  Riyousuke AKAZAWA ,  Takefumi TAKAHASHI ,  Masahiro WAKASHIMA ,  Yuta KUROSU ,  Akito MORI

IPC: H01G4/30 ,  H01G4/012 ,  H01G4/008 ,  H01G4/12

CPC classification number: H01G4/30 ,  H01G4/012 ,  H01G4/008 ,  H01G4/1218

Abstract: A multilayer ceramic capacitor includes a multilayer body including dielectric layers and internal electrode layers alternately laminated therein, and external electrode layers respectively provided on both end surfaces of the multilayer body in a length direction intersecting a lamination direction, and each connected to the internal electrode layers, the external electrode layers each further including a base electrode layer including a first region, a second region, and a third region divided therein, in order from the multilayer body. The first region includes a metal included in the internal electrode layers in a higher amount than the second region and the third region, the second region includes glass in a higher amount than the first region and the third region, and the third region includes copper in a higher amount than the first region and the second region.

公开(公告)号：US20220068566A1

公开(公告)日：2022-03-03

申请号：US17378822

申请日：2021-07-19

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Syouta IKEBE ,  Yasuhiro NISHISAKA ,  Takefumi TAKAHASHI

IPC: H01G4/30 ,  H01G4/012 ,  H01G4/12 ,  H01G4/008 ,  H01G4/08

Abstract: A multilayer ceramic electronic component includes a multilayer body and an outer electrode on each end surfaces of the multilayer body. The outer electrode includes an underlying electrode layer and a plating layer on the underlying electrode layer. Void portions inside the underlying electrode layer are each filled with a barrier film. The barrier film is formed by an atomic layer deposition method.

公开(公告)号：US20240355552A1

公开(公告)日：2024-10-24

申请号：US18760090

申请日：2024-07-01

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Keita KITAHARA ,  Masahiro WAKASHIMA ,  Takefumi TAKAHASHI ,  Yuuta TAKAGI ,  Syouta IKEBE

IPC: H01G4/30 ,  H01G2/06 ,  H01G4/008 ,  H01G4/012 ,  H01G4/12

CPC classification number: H01G4/30 ,  H01G2/065 ,  H01G4/008 ,  H01G4/012 ,  H01G4/1227

Abstract: A multilayer ceramic capacitor includes a multilayer body including dielectric layers and internal electrode layers alternately laminated, and external electrodes each on a corresponding one of two end surfaces opposed to each other in a length direction perpendicular or substantially perpendicular to a lamination direction of the multilayer body. The external electrodes are each connected to the internal electrode layers. Each of the external electrodes includes a stack including a base electrode layer on a corresponding one of the two end surfaces, a Ni plated layer on the base electrode layer, and a Sn plated layer on the Ni plated layer. Each of the external electrodes includes a region in which Sn is deposited between the base electrode layer and the Ni plated layer.