-
公开(公告)号：US20250150043A1
公开(公告)日：2025-05-08
申请号：US18926642
申请日：2024-10-25
Applicant: MURATA MANUFACTURING CO., LTD.
Inventor： Makoto TABEI
IPC: H03F3/21
Abstract: A power amplifier circuit includes: a first switch circuit that switches conduction and non-conduction between a node between the drive stage amplifier and the power stage amplifier and an output terminal, and a second switch circuit that switches conduction and non-conduction between the power stage amplifier and the output terminal. The power amplifier circuit has a first mode in which the first switch circuit is made conductive and the second switch circuit is made non-conductive, and a second mode in which the first switch circuit is made non-conductive and the second switch circuit is made conductive. The power amplifier circuit makes, when shifting from the first mode to the second mode, the first switch circuit non-conductive after making the second switch circuit conductive, and makes, when shifting from the second mode to the first mode, the second switch circuit non-conductive after making the first switch circuit conductive.
-
公开(公告)号：US20210058040A1
公开(公告)日：2021-02-25
申请号：US17078189
申请日：2020-10-23
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Makoto TABEI , Ken WAKAKI , Masamichi TOKUDA , Daisuke WATANABE
Abstract: An amplifier circuit amplifies a radio-frequency signal. The amplifier circuit includes an amplifier, an input matching circuit connected to an input side of the amplifier and matches impedance, and a protection circuit connected to a node in a path within a path between an input matching circuit and the amplifier. The protection circuit includes a first diode connected between the node and a ground, and a second diode connected in parallel with the first diode and connected in a direction opposite to the first diode between the node and the ground. A threshold voltage of each of the first diode and the second diode is greater than a maximum voltage amplitude of the input signal at the node and is less than a difference between a withstand voltage of the amplifier and the bias voltage.
-
公开(公告)号：US20240291449A1
公开(公告)日：2024-08-29
申请号：US18584365
申请日：2024-02-22
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Makoto TABEI , Kenji FURUSAWA
CPC classification number: H03F3/245 , H03F1/0205 , H03F2200/451
Abstract: An amplifier circuit includes: an input terminal; a first FET having a gate; a second FET connected, together with the first FET, between a power supply and a reference potential; an output terminal provided between the second FET and a load to output an amplified signal; a first voltage divider resistor circuit that divides a potential difference between the power supply and the reference potential, and generates a bias to be applied to a gate of the second FET; and a first switch element provided between the first voltage divider resistor circuit and the power supply and for turning on/off an electrical connection between the power supply and the first voltage divider resistor circuit. The first FET and the second FET have their adjacent drains and sources connected. The first switch element turns off when amplification operation by the first FET and the second FET is not performed.
-
公开(公告)号：US20240283408A1
公开(公告)日：2024-08-22
申请号：US18441038
申请日：2024-02-14
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Makoto TABEI
CPC classification number: H03F1/301 , H03F1/0222 , H03F3/21 , H03F2200/441
Abstract: An amplification circuit includes an input terminal to which a signal to be amplified is input, a first FET having a gate to which a signal input to the input terminal is applied, second and third FETs that are connected between a power supply and a reference potential, an output terminal that is provided between a load and the third FET nearest to the power supply and configured to output an amplified signal, a voltage-dividing resistor circuit configured to generate a bias to be applied to gates of the second and third FETs, and a clamping circuit configured to clamp a bias to be applied to the gate of the third FET when a bias to be applied from the voltage-dividing resistor circuit to the gate of the second FET exceeds a predetermined reference voltage. The first to third FETS are vertically stacked and connected.
-
Patent Agency Ranking
公开(公告)号：US20210226587A1
公开(公告)日：2021-07-22
申请号：US17151805
申请日：2021-01-19
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Takashi KAWANAMI , Makoto TABEI
Abstract: An amplifier circuit includes: a transistor provided between an input terminal and an output terminal and having a gate connected to the input terminal, a source connected to a ground, and a drain connected to the output terminal; an inductor connected between the source and the ground; an inductor connected between the gate and the input terminal, and switches connected to at least one of the inductors and configured to change a mutual inductance of the inductors.
-
公开(公告)号：US20240291450A1
公开(公告)日：2024-08-29
申请号：US18586938
申请日：2024-02-26
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Makoto TABEI
CPC classification number: H03F3/245 , H03F1/56 , H03F2200/387
Abstract: An amplifier circuit includes: a second FET connected, together with a first FET, between a power supply and a reference potential; a first voltage divider resistor circuit; a first switch element; a second voltage divider resistor circuit; a third voltage divider resistor circuit; and a second switch element. The first FET and the second FET have their adjacent drains and sources connected. Each resistance value of the second voltage divider resistor circuit is greater than each resistance value of the first voltage divider resistor circuit. Each resistance value of the third voltage divider resistor circuit is less than each resistance value of the second voltage divider resistor circuit. The second voltage divider resistor circuit and the third voltage divider resistor circuit have an identical voltage division ratio.
-
公开(公告)号：US20240097674A1
公开(公告)日：2024-03-21
申请号：US18461749
申请日：2023-09-06
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Makoto TABEI
IPC: H03K17/56 , H03K5/1252
CPC classification number: H03K17/56 , H03K5/1252
Abstract: A switching circuit includes: a substrate including input-and-output terminals; a switch provided to the substrate and including a source terminal, a gate terminal, and a drain terminal, the source terminal being connected to an input end of a power amplifier, the drain terminal being connected to a first input-and-output terminal; a voltage control circuit provided to the substrate and connected to the gate terminal; a switch provided to the substrate and including a source terminal, a gate terminal, and a drain terminal, the source terminal being connected to a second input-and-output terminal, the drain terminal being connected to an output end of the power amplifier; and a voltage control circuit provided to the substrate to be apart from the voltage control circuit and connected to the gate terminal.
-
公开(公告)号：US20230336129A1
公开(公告)日：2023-10-19
申请号：US18337532
申请日：2023-06-20
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Makoto TABEI
IPC: H03F1/52
Abstract: An amplifier circuit includes an input terminal, an output terminal, a transistor provided in between the input terminal and the output terminal, and a coiled or meandered inductor. The transistor has a gate, a source, and a drain, and of these gate, source, and drain, two terminals are connected to ground terminals that are different from each other. The inductor is connected between the ground terminals to which the foregoing two terminals are connected.
-
公开(公告)号：US20220069777A1
公开(公告)日：2022-03-03
申请号：US17401539
申请日：2021-08-13
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Tsutomu OONARO , Masamichi TOKUDA , Makoto TABEI , Kazuaki DEGUCHI , Takayuki KAWANO
Abstract: An amplifier device includes an amplifier including cascade-connected power amplifiers in a plurality of stages and a bias circuit configured to supply bias currents to the amplifier. A bias current supplied to a power amplifier in the first stage of the power amplifiers in the plurality of stages exhibits a positive temperature characteristic. A bias current supplied to a power amplifier in the final stage exhibits a negative temperature characteristic.
-
-
-
-
-
-
-
-
Search Results
9
records
(took 0.016 seconds)
