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    Cache access control system
    1.
    发明授权
    Cache access control system 失效
    缓存访问控制系统

    公开(公告)号：US06484242B2

    公开(公告)日：2002-11-19

    申请号：US09809217

    申请日：2001-03-16

    申请人： Mutsumi Hosoya ,  Michitaka Yamamoto

    发明人： Mutsumi Hosoya ,  Michitaka Yamamoto

    IPC分类号： G06F1202

    CPC分类号： G06F12/0811

    摘要： A cache access control system for dynamically conducting specification of dedicated and common regions and thereby always conducting optimum cache coherency control. In a processor, an L1 cache including an L1 data array and a directory is provided. A plurality of L2 caches are connected to each L1 cache. The L2 caches are connected to a main memory L3. An L2 cache history manager is supplied with L2 cache status information and an L2 cache access request from L2 caches. The L2 cache history manager judges an attribute (a dedicated region or a common region) of each line of L2. On the basis of the attribute, a cache coherency manager conducts coherency control of each L2 cache by using an invalidation type protocol or an update type protocol. The attribute is judged to be the common region, only in the case where a line shared by a plurality of L2 caches in the past is canceled once by the invalidation type protocol and then accessed again.

    摘要翻译： 高速缓存存取控制系统，用于动态地执行专用和公共区域的规范，从而始终执行最佳高速缓存一致性控制。 在处理器中，提供包括L1数据阵列和目录的L1高速缓存。 多个L2高速缓存连接到每个L1高速缓存。 L2高速缓存连接到主存储器L3。 二级缓存历史管理器提供二级高速缓存状态信息和二级高速缓存访​​问请求。 L2缓存历史管理器判断L2的每一行的属性（专用区域或公共区域）。 基于该属性，高速缓存一致性管理器通过使用无效类型协议或更新类型协议来执行每个L2高速缓存的一致性控制。 该属性被判断为公共区域，仅在过去的多个L2高速缓存共享的行被无效化协议一次取消然后再次访问的情况下。

    Micro program control method and apparatus thereof having branch instructions
    2.
    发明授权
    Micro program control method and apparatus thereof having branch instructions 失效
    微程序控制方法及其具有分支指令的装置

    公开(公告)号：US06715065B1

    公开(公告)日：2004-03-30

    申请号：US09539898

    申请日：2000-03-31

    申请人： Atsushi Ebata ,  Michitaka Yamamoto ,  Takeshi Kato

    发明人： Atsushi Ebata ,  Michitaka Yamamoto ,  Takeshi Kato

    IPC分类号： G06F900

    CPC分类号： G06F9/264

    摘要： In an information processing apparatus which executes micro programs having branch instructions, two micro instructions are read at once, each of which instructions comprises either a field for specifying the branch target address in the following Nth (N≧2) cycle from the reading cycle of the micro instruction, or a field for determining the termination of micro program in the following Nth (N≧2) cycle, and a control field for controlling the execution in the next cycle.

    摘要翻译： 在执行具有分支指令的微程序的信息处理装置中，一次读取两个微指令，每个指令包括从读取周期起的第N（N> = 2）个循环中指定分支目标地址的字段 或用于确定在下一个第N（N> = 2）周期中的微程序的终止的字段，以及用于在下一个周期中控制执行的控制字段。

    Multiple virtual addressing using/comparing translation pairs of addresses comprising a space address and an origin address (STO) while using space registers as storage devices for a data processing system
    4.
    发明授权
    Multiple virtual addressing using/comparing translation pairs of addresses comprising a space address and an origin address (STO) while using space registers as storage devices for a data processing system 失效
    在使用空间寄存器作为数据处理系统的存储设备时，使用/比较包含空格地址和原始地址（STO）的地址的翻译对的多个虚拟寻址

    公开(公告)号：US5226132A

    公开(公告)日：1993-07-06

    申请号：US413444

    申请日：1989-09-27

    申请人： Michitaka Yamamoto ,  Toshinori Kuwabara ,  Yoshio Oshima ,  Yasutaka Yamada

    发明人： Michitaka Yamamoto ,  Toshinori Kuwabara ,  Yoshio Oshima ,  Yasutaka Yamada

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0292

    摘要： Instead of translation from a space address to a segment table origin address (STO) by an ordinary instruction, translation to the STO is done by a space base register modify instruction which uses an instruction to modify the content of the space register, and the result thereof is used for the operand address calculation of the instruction to the operand data fetching. The present system eliminates the need for additionally providing for hardware of an operand fetch unit hardware for the translation from the space address to the STO, memory for storing translation pairs of the space addresses and the STO's and the table look-up of the translation pairs. Thus, degradation of performance is minimized with less hardware.

    摘要翻译： 代替通过普通指令从空间地址到段表原点地址（STO）的转换，通过使用修改空间寄存器的内容的指令的空间基地址寄存器修改指令来进行到STO的转换，结果 用于对操作数数据取出指令的操作数地址计算。 本系统不需要另外提供用于从空间地址到STO的转换的操作数获取单元硬件的硬件，用于存储空间地址和STO的转换对的存储器以及翻译对的表查找 。 因此，通过较少的硬件使性能下降最小化。

    Dynamic logic circuit and integrated circuit device using the logic circuit
    5.
    发明授权
    Dynamic logic circuit and integrated circuit device using the logic circuit 失效
    动态逻辑电路和集成电路器件采用逻辑电路

    公开(公告)号：US06278296B1

    公开(公告)日：2001-08-21

    申请号：US09369199

    申请日：1999-08-06

    申请人： Noboru Masuda ,  Michitaka Yamamoto

    发明人： Noboru Masuda ,  Michitaka Yamamoto

    IPC分类号： H03K19096

    CPC分类号： H03K19/0963

    摘要： In a dynamic logic circuit, a signal delay time between a low-to-high transition of an input signal and a low-to-high transition of an output signal is reduced, a through current is decreased and a time required for the precharge is reduced. In the dynamic logic circuit a P-channel type MOS transistor (PMOS) has its source electrode connected with a power supply on the side of a high voltage potential Vdd. Its gate electrode receives a clock signal Cs. A logic portion includes N-channel type MOS transistors (NMOS) connected between a drain electrode of the PMOS and a power supply on the side of a low voltage potential Vss. An NMOS is provided between an input signal connected with a NMOS closest to the Vss in the NMOSs and the Vss. A reverse signal of the clock signal Cs is connected with a gate electrode of the NMOS. An input signal is forced to change to a low level at the time of the precharge, thereby a through current is decreased and a time required for the precharge is reduced. Therefore, a signal delay time is reduced.

    摘要翻译： 在动态逻辑电路中，输入信号的从低到高跃迁与输出信号的低电平到高转换之间的信号延迟时间减小，直流电流减小，预充电所需的时间为 减少 在动态逻辑电路中，P沟道型MOS晶体管（PMOS）的源电极与高压电位Vdd侧的电源连接。 其栅电极接收时钟信号Cs。 逻辑部分包括连接在PMOS的漏电极和低电压电位Vss侧的电源之间的N沟道型MOS晶体管（NMOS）。 在与NMOS中的最接近Vss的NMOS连接的输入信号和Vss之间提供NMOS。 时钟信号Cs的反向信号与NMOS的栅电极连接。 在预充电时强制输入信号变为低电平，从而减小通电流，并减少预充电所需的时间。 因此，信号延迟时间减少。