公开(公告)号：US06875690B2

公开(公告)日：2005-04-05

申请号：US10625027

申请日：2003-07-22

申请人： Myeong-Cheol Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Seung-Young Son

发明人： Myeong-Cheol Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Seung-Young Son

IPC分类号： H01L21/28 ,  H01L21/60 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/108 ,  H01L21/44

CPC分类号： H01L21/76831 ,  H01L21/76897 ,  H01L23/5226 ,  H01L27/10814 ,  H01L27/10855 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a semiconductor device having a self-aligned contact plug and a method of fabricating the semiconductor device. The semiconductor device includes conductive patterns, a first interlayer insulating layer, a first spacer, a second interlayer insulating layer, and a contact plug. In each conductive pattern, a conductive layer and a capping layer are sequentially deposited on an insulating layer over a semiconductor substrate. The first interlayer insulating layer fills spaces between the conductive patterns and has a height such that when the first interlayer insulating layer is placed on the insulating layer, the first interlayer insulating layer is lower than a top surface of the capping layer but higher than a top surface of the conductive layer. The first spacer surrounds the outer surface of the capping layer on the first interlayer insulating layer. The second interlayer insulating layer covers the first interlayer insulating layer, the capping layer, and the first spacer and has a planarized top surface. The contact plug passes through the second interlayer insulating layer, the first interlayer insulating layer, and the insulating layer between the conductive patterns, is electrically connected to the semiconductor substrate, has an outerwall surrounded by a second spacer, and is self-aligned with the capping layer.

摘要翻译： 提供一种具有自对准接触插塞的半导体器件和制造半导体器件的方法。 半导体器件包括导电图案，第一层间绝缘层，第一间隔物，第二层间绝缘层和接触塞。 在每个导电图案中，导电层和覆盖层依次沉积在半导体衬底上的绝缘层上。 第一层间绝缘层填充导电图案之间的空间，并且具有这样的高度，使得当第一层间绝缘层放置在绝缘层上时，第一层间绝缘层低于封盖层的顶表面，但高于顶部 导电层的表面。 第一间隔件包围第一层间绝缘层上的覆盖层的外表面。 第二层间绝缘层覆盖第一层间绝缘层，覆盖层和第一间隔物，并且具有平坦化的顶表面。 接触插塞穿过第二层间绝缘层，第一层间绝缘层和导电图案之间的绝缘层电连接到半导体衬底，具有由第二间隔物包围的外壁，并且与 盖层

公开(公告)号：US20050158948A1

公开(公告)日：2005-07-21

申请号：US11058670

申请日：2005-02-15

申请人： Myeong-Cheol Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Seung-Young Son

发明人： Myeong-Cheol Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Seung-Young Son

IPC分类号： H01L21/28 ,  H01L21/60 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/108

CPC分类号： H01L21/76831 ,  H01L21/76897 ,  H01L23/5226 ,  H01L27/10814 ,  H01L27/10855 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a semiconductor device having a self-aligned contact plug and a method of fabricating the semiconductor device. The semiconductor device includes conductive patterns, a first interlayer insulating layer, a first spacer, a second interlayer insulating layer, and a contact plug. In each conductive pattern, a conductive layer and a capping layer are sequentially deposited on an insulating layer over a semiconductor substrate. The first interlayer insulating layer fills spaces between the conductive patterns and has a height such that when the first interlayer insulating layer is placed on the insulating layer, the first interlayer insulating layer is lower than a top surface of the capping layer but higher than a top surface of the conductive layer. The first spacer surrounds the outer surface of the capping layer on the first interlayer insulating layer. The second interlayer insulating layer covers the first interlayer insulating layer, the capping layer, and the first spacer and has a planarized top surface. The contact plug passes through the second interlayer insulating layer, the first interlayer insulating layer, and the insulating layer between the conductive patterns, is electrically connected to the semiconductor substrate, has an outerwall surrounded by a second spacer, and is self-aligned with the capping layer.

公开(公告)号：US07256143B2

公开(公告)日：2007-08-14

申请号：US11058670

申请日：2005-02-15

申请人： Myeong-Cheol Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Seung-Young Son

发明人： Myeong-Cheol Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Seung-Young Son

IPC分类号： H01L21/31

CPC分类号： H01L21/76831 ,  H01L21/76897 ,  H01L23/5226 ,  H01L27/10814 ,  H01L27/10855 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a semiconductor device having a self-aligned contact plug and a method of fabricating the semiconductor device. The semiconductor device includes conductive patterns, a first interlayer insulating layer, a first spacer, a second interlayer insulating layer, and a contact plug. In each conductive pattern, a conductive layer and a capping layer are sequentially deposited on an insulating layer over a semiconductor substrate. The first interlayer insulating layer fills spaces between the conductive patterns and has a height such that when the first interlayer insulating layer is placed on the insulating layer, the first interlayer insulating layer is lower than a top surface of the capping layer but higher than a top surface of the conductive layer. The first spacer surrounds the outer surface of the capping layer on the first interlayer insulating layer. The second interlayer insulating layer covers the first interlayer insulating layer, the capping layer, and the first spacer and has a planarized top surface. The contact plug passes through the second interlayer insulating layer, the first interlayer insulating layer, and the insulating layer between the conductive patterns, is electrically connected to the semiconductor substrate, has an outerwall surrounded by a second spacer, and is self-aligned with the capping layer.

摘要翻译： 提供一种具有自对准接触插塞的半导体器件和制造半导体器件的方法。 半导体器件包括导电图案，第一层间绝缘层，第一间隔物，第二层间绝缘层和接触塞。 在每个导电图案中，导电层和覆盖层依次沉积在半导体衬底上的绝缘层上。 第一层间绝缘层填充导电图案之间的空间，并且具有这样的高度，使得当第一层间绝缘层放置在绝缘层上时，第一层间绝缘层低于封盖层的顶表面，但高于顶部 导电层的表面。 第一间隔件包围第一层间绝缘层上的覆盖层的外表面。 第二层间绝缘层覆盖第一层间绝缘层，覆盖层和第一间隔物，并且具有平坦化的顶表面。 接触插塞穿过第二层间绝缘层，第一层间绝缘层和导电图案之间的绝缘层电连接到半导体衬底，具有由第二间隔物包围的外壁，并且与 盖层

公开(公告)号：US20050003310A1

公开(公告)日：2005-01-06

申请号：US10802150

申请日：2004-03-17

申请人： Keun-Hee Bai ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Myeong-Cheol Kim

发明人： Keun-Hee Bai ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Myeong-Cheol Kim

IPC分类号： H01L21/3065 ,  G03F7/36 ,  G03F7/40 ,  H01L21/027 ,  H01L21/311

CPC分类号： G03F7/40 ,  H01L21/0276 ,  H01L21/31144

摘要： An etching process including plasma pretreatment for generating a polymer layer formed of carbon on a photoresist pattern. The photoresist pattern is treated with plasma that does not contain fluorine radicals and that provides carbon radicals. An etching process is performed on an etching target layer by using the photoresist pattern as an etch mask.

摘要翻译： 一种蚀刻工艺，包括用于在光致抗蚀剂图案上产生由碳形成的聚合物层的等离子体预处理。 用不含氟自由基并提供碳自由基的等离子体处理光致抗蚀剂图案。 通过使用光致抗蚀剂图案作为蚀刻掩模，在蚀刻目标层上进行蚀刻处理。

公开(公告)号：US20050001252A1

公开(公告)日：2005-01-06

申请号：US10858727

申请日：2004-06-02

申请人： Yong-Jin Kim ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Myeong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

发明人： Yong-Jin Kim ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Myeong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L29/66621 ,  H01L21/823437 ,  H01L27/10876 ,  H01L29/7834

摘要： A semiconductor device includes a plurality of gate trenches, each of which has first inner walls, which face each other in a first direction which is perpendicular to a second direction in which active regions extend, and second inner walls, which face each other in the second direction in which the active regions extends. An isolation layer contacts a gate insulating layer throughout the entire length of the first inner walls of the gate trenches including from entrance portions of the gate trenches to bottom portions of the gate trenches, and a plurality of channel regions are disposed adjacent to the gate insulating layers in the semiconductor substrate along the second inner walls and the bottom portions of the gate trenches.

摘要翻译： 半导体器件包括多个栅极沟槽，每个栅极沟槽具有第一内壁，该第一内壁沿与第一方向相对的第一方向，该第一方向垂直于有源区域延伸的第二方向;以及第二内壁， 活动区域延伸的第二方向。 隔离层在包括从栅极沟槽的入口部分到栅极沟槽的底部的栅极沟槽的整个长度的整个长度上接触栅极绝缘层，并且多个沟道区域邻近栅极绝缘体 沿着第二内壁和栅极沟槽的底部的半导体衬底中的层。

公开(公告)号：US07183600B2

公开(公告)日：2007-02-27

申请号：US10858727

申请日：2004-06-02

申请人： Yong-Jin Kim ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Myeong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

发明人： Yong-Jin Kim ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Myeong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

IPC分类号： H01L29/76

CPC分类号： H01L29/66621 ,  H01L21/823437 ,  H01L27/10876 ,  H01L29/7834

摘要： A semiconductor device includes a plurality of gate trenches, each of which has first inner walls, which face each other in a first direction which is perpendicular to a second direction in which active regions extend, and second inner walls, which face each other in the second direction in which the active regions extends. An isolation layer contacts a gate insulating layer throughout the entire length of the first inner walls of the gate trenches including from entrance portions of the gate trenches to bottom portions of the gate trenches, and a plurality of channel regions are disposed adjacent to the gate insulating layers in the semiconductor substrate along the second inner walls and the bottom portions of the gate trenches.

摘要翻译： 半导体器件包括多个栅极沟槽，每个栅极沟槽具有第一内壁，该第一内壁沿与第一方向相对的第一方向，该第一方向垂直于有源区域延伸的第二方向;以及第二内壁， 活动区域延伸的第二方向。 隔离层在包括从栅极沟槽的入口部分到栅极沟槽的底部的栅极沟槽的整个长度的整个长度上接触栅极绝缘层，并且多个沟道区域邻近栅极绝缘体 沿着第二内壁和栅极沟槽的底部的半导体衬底中的层。

公开(公告)号：US20080087931A1

公开(公告)日：2008-04-17

申请号：US11869400

申请日：2007-10-09

申请人： Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

发明人： Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

IPC分类号： H01L27/108 ,  H01L21/3205 ,  H01L21/8242

CPC分类号： H01L28/91 ,  H01L21/3142 ,  H01L21/31616 ,  H01L21/31645 ,  H01L21/32136 ,  H01L27/10855

摘要： Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer, forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.

摘要翻译： 提供了用于制造具有电容器的半导体器件的方法，其阻止电容器的下部电极断开或塌缩并且提供电容器的增加的电容。 例如，一种方法包括在半导体衬底上形成第一绝缘层，在第一绝缘层中形成第一孔，在第一孔中形成接触塞，形成具有着陆垫的第二绝缘层，其中， 所述接触插塞的上表面在所述着陆焊盘和所述第二绝缘层上形成蚀刻停止层，在所述蚀刻停止层上形成第三绝缘层，形成通过所述第三绝缘层的第三孔和蚀刻停止层， 选择性地蚀刻暴露的着陆焊盘，在选择性蚀刻的着陆焊盘上形成下电极，然后通过在下电极上形成电介质层和上电极来形成电容器。

公开(公告)号：US07736970B2

公开(公告)日：2010-06-15

申请号：US11869400

申请日：2007-10-09

申请人： Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

发明人： Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

IPC分类号： H01L21/8242

CPC分类号： H01L28/91 ,  H01L21/3142 ,  H01L21/31616 ,  H01L21/31645 ,  H01L21/32136 ,  H01L27/10855

摘要： Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer, forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.

摘要翻译： 提供了用于制造具有电容器的半导体器件的方法，其阻止电容器的下部电极断开或塌缩并且提供电容器的增加的电容。 例如，一种方法包括在半导体衬底上形成第一绝缘层，在第一绝缘层中形成第一孔，在第一孔中形成接触塞，形成具有着陆垫的第二绝缘层，其中， 所述接触插塞的上表面在所述着陆焊盘和所述第二绝缘层上形成蚀刻停止层，在所述蚀刻停止层上形成第三绝缘层，形成通过所述第三绝缘层的第三孔和蚀刻停止层， 选择性地蚀刻暴露的着陆焊盘，在选择性蚀刻的着陆焊盘上形成下电极，然后通过在下电极上形成电介质层和上电极来形成电容器。

公开(公告)号：US20050130371A1

公开(公告)日：2005-06-16

申请号：US11048995

申请日：2005-02-02

申请人： Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

发明人： Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

IPC分类号： H01L21/8242 ,  H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/3213

CPC分类号： H01L28/91 ,  H01L21/3142 ,  H01L21/31616 ,  H01L21/31645 ,  H01L21/32136 ,  H01L27/10855

摘要： Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer; forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.

公开(公告)号：US06867096B2

公开(公告)日：2005-03-15

申请号：US10855165

申请日：2004-05-27

申请人： Sung-IL Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

发明人： Sung-IL Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

IPC分类号： H01L21/8242 ,  H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/3213

CPC分类号： H01L28/91 ,  H01L21/3142 ,  H01L21/31616 ,  H01L21/31645 ,  H01L21/32136 ,  H01L27/10855

摘要： Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer; forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.

摘要翻译： 提供了用于制造具有电容器的半导体器件的方法，其阻止电容器的下部电极断开或塌缩并且提供电容器的增加的电容。 例如，一种方法包括在半导体衬底上形成第一绝缘层，在第一绝缘层中形成第一孔，在第一孔中形成接触塞，形成具有着陆垫的第二绝缘层，其中， 接触插塞的上表面，在着陆焊盘和第二绝缘层上形成蚀刻停止层，在蚀刻停止层上形成第三绝缘层; 通过第三绝缘层和蚀刻停止层形成第三孔以暴露着陆焊盘，选择性地蚀刻暴露的着陆焊盘，在选择性蚀刻的焊盘上形成下电极，然后通过形成电介质层和上层 电极在下电极上。