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238 条记录 (耗时 0.029 秒)

    Low noise and high performance LSI device
    8.
    发明授权
    Low noise and high performance LSI device 有权
    低噪声，高性能的LSI器件

    公开(公告)号：US08816440B2

    公开(公告)日：2014-08-26

    申请号：US12984261

    申请日：2011-01-04

    申请人： Shigenobu Maeda ,  Jeong Hwan Yang

    发明人： Shigenobu Maeda ,  Jeong Hwan Yang

    IPC分类号： H01L29/94 ,  H01L31/062 ,  H01L31/113

    CPC分类号： H01L27/0922 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/1052 ,  H01L29/0649 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848

    摘要： In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate. For example, mechanical stress can be applied to devices that operate in high-speed digital settings, while devices that operate in analog or RF signal settings, in which electrical noise such as flicker noise that may be introduced by applied stress may degrade performance, have no stress applied.

    摘要翻译： 在其中使用NMOS器件和PMOS器件的半导体器件中，以不同的模式（例如模拟和数字模式）来执行应力工程，根据所需的操作模式，对特定器件有选择地施加应力工程。 也就是说，适当的机械应力，即拉伸或压缩，可以施加到和/或从设备（即，NMOS和/或PMOS器件）中去除和/或从器件去除，不仅基于它们的导电类型，即n型或p- 类型，而且还在于其预期的操作应用，例如模拟/数字，低电压/高电压，高速/低速，噪声敏感/噪声不敏感等。结果是个体的性能 设备根据其运行模式进行优化。 例如，机械应力可以应用于在高速数字设置中工作的设备，而在模拟或RF信号设置中工作的设备，其中可能由施加的应力引入的诸如闪烁噪声的电噪声可能降低性能，具有 没有施加应力。

    Semiconductor MIS transistor formed on SOI semiconductor substrate
    9.
    发明授权
    Semiconductor MIS transistor formed on SOI semiconductor substrate 有权
    半导体MIS晶体管形成在SOI半导体衬底上

    公开(公告)号：US07531878B2

    公开(公告)日：2009-05-12

    申请号：US11610932

    申请日：2006-12-14

    申请人： Shigenobu Maeda ,  Shigeto Maegawa ,  Takuji Matsumoto

    发明人： Shigenobu Maeda ,  Shigeto Maegawa ,  Takuji Matsumoto

    IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

    CPC分类号： H01L29/045 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1087 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78615 ,  H01L29/78621 ,  H01L29/78654 ,  H01L29/78687 ,  H01L29/78696

    摘要： There is provided a semiconductor device which is formed on a semiconductor substrate and allows effective use of the feature of the semiconductor substrate, and there is also provided a method of manufacturing the same. An N-channel MOS transistor including a P-type body layer (3a), and a P-type active layer (6) for body voltage application which is in contact with the P-type body layer (3a) are formed on an SOI substrate which is formed to align a crystal direction of a support substrate (1) with a crystal direction of an SOI layer (3). A path connecting the P-type body layer (3a) and the P-type active layer (6) for body voltage application is aligned parallel to the crystal direction of the SOI layer (3). Since hole mobility is higher in the crystal direction, parasitic resistance (Ra, Rb) can be reduced in the above path. This speeds up voltage transmission to the P-type body layer (3a) and improves voltage fixing capability in the P-type body layer (3a).

    摘要翻译： 提供一种半导体器件，其形成在半导体衬底上并且有效地利用了半导体衬底的特征，并且还提供了一种制造该半导体衬底的方法。 包括P型体层（3a）和与P型体层（3a）接触的体电压施加用P型有源层（6）的N沟道MOS晶体管形成在SOI 衬底，其被形成为使支撑衬底（1）的<110>晶体方向与SOI层（3）的<100>晶体方向对准。 连接P型体层（3a）和用于体电压施加的P型有源层（6）的路径平行于SOI层（3）的<100>晶体方向排列。 由于在<100>晶体方向的空穴迁移率较高，所以在上述路径中可以减小寄生电阻（Ra，Rb）。 这加快了P型体层（3a）的电压传输，提高了P型体层（3a）的电压固定能力。

    Semiconductor device including insulated gate type transistor and insulated gate type variable capacitance, and method of manufacturing the same
    10.
    发明授权
    Semiconductor device including insulated gate type transistor and insulated gate type variable capacitance, and method of manufacturing the same 失效
    包括绝缘栅型晶体管和绝缘栅型可变电容的半导体器件及其制造方法

    公开(公告)号：US07456464B2

    公开(公告)日：2008-11-25

    申请号：US11621177

    申请日：2007-01-09

    申请人： Shigenobu Maeda ,  Hiroyuki Takashino ,  Toshihide Oka

    发明人： Shigenobu Maeda ,  Hiroyuki Takashino ,  Toshihide Oka

    IPC分类号： H01L29/94

    CPC分类号： H01L21/26586 ,  H01L21/74 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/0808 ,  H01L27/0811 ,  H01L27/1203 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/94

    摘要： It is an object to obtain a semiconductor device having such a structure that respective electrical characteristics of an insulated gate type transistor and an insulated gate type capacitance are not deteriorated and a method of manufacturing the semiconductor device. An NMOS transistor Q1 and a PMOS transistor Q2 which are formed in an NMOS formation region A1 and a PMOS formation region A2 respectively have P−pocket regions 17 and N−pocket regions 27 in vicinal regions of extension portions 14e and 24e of N+ source-drain regions 14 and P+source-drain regions 24, respectively. On the other hand, an N-type variable capacitance C1 and a P-type variable capacitance C2 which are formed in an N-type variable capacitance formation region A3 and a P-type variable capacitance formation region A4 respectively do not have a region of a reverse conductivity type which is adjacent to extraction electrode regions corresponding to the P−pocket regions 17 and the N−pocket regions 27.

    摘要翻译： 本发明的目的是获得具有绝缘栅型晶体管和绝缘栅型电容的各自电特性不劣化的结构的半导体器件以及半导体器件的制造方法。 形成在NMOS形成区域A 1和PMOS形成区域A 2中的NMOS晶体管Q 1和PMOS晶体管Q 2分别具有P 0〜 分别为N +源极 - 漏极区域14和P +源极 - 漏极区域24的延伸部分14e和24e的连续区域中的多个区域27。 另一方面，形成在N型可变电容形成区域A 3和P型可变电容形成区域A 4中的N型可变电容C 1和P型可变电容C 2分别不 具有与对应于凹穴区域17和凹陷区域27的引出电极区域相邻的反向导电型区域。