公开(公告)号：US09431537B2

公开(公告)日：2016-08-30

申请号：US14669082

申请日：2015-03-26

申请人： Shigenobu Maeda ,  Tae-Yong Kwon ,  Sang-Su Kim ,  Jae-Hoo Park

发明人： Shigenobu Maeda ,  Tae-Yong Kwon ,  Sang-Su Kim ,  Jae-Hoo Park

IPC分类号： H01L31/072 ,  H01L31/109 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L27/092 ,  H01L29/165

CPC分类号： H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

摘要： Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer. A dummy gate pattern that intersects the fin-type active pattern and that extends in a second direction that is different from the first direction is formed. The methods include forming dummy gate spacers on side walls of the dummy gate pattern, forming recesses in the fin-type active pattern on both sides of the dummy gate pattern and forming source and drain regions on both sides of the dummy gate pattern.

摘要翻译： 形成半导体器件的方法可以包括形成在衬底上沿第一方向延伸的鳍式有源图案，鳍型有源图案包括在衬底上的下图案和下图案上的上图案。 场绝缘层形成在衬底上，翅片型有源图案的侧壁和远离衬底的部分上部图案远离场绝缘层的顶表面。 形成与翅片型有源图案相交并且沿与第一方向不同的第二方向延伸的伪栅极图案。 所述方法包括在伪栅极图案的侧壁上形成虚拟栅极间隔物，在虚拟栅极图案的两侧上形成鳍状有源图案中的凹槽，并在虚拟栅极图案的两侧形成源区和漏极区。

公开(公告)号：US20150279995A1

公开(公告)日：2015-10-01

申请号：US14669082

申请日：2015-03-26

申请人： Shigenobu Maeda ,  Tae-Yong Kwon ,  Sang-Su Kim ,  Jae-Hoo Park

发明人： Shigenobu Maeda ,  Tae-Yong Kwon ,  Sang-Su Kim ,  Jae-Hoo Park

IPC分类号： H01L29/78 ,  H01L27/092

CPC分类号： H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

摘要： Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer. A dummy gate pattern that intersects the fin-type active pattern and that extends in a second direction that is different from the first direction is formed. The methods include forming dummy gate spacers on side walls of the dummy gate pattern, forming recesses in the fin-type active pattern on both sides of the dummy gate pattern and forming source and drain regions on both sides of the dummy gate pattern.

摘要翻译： 形成半导体器件的方法可以包括形成在衬底上沿第一方向延伸的鳍式有源图案，鳍型有源图案包括在衬底上的下图案和下图案上的上图案。 场绝缘层形成在衬底上，翅片型有源图案的侧壁和远离衬底的部分上部图案远离场绝缘层的顶表面。 形成与翅片型有源图案相交并且沿与第一方向不同的第二方向延伸的伪栅极图案。 所述方法包括在伪栅极图案的侧壁上形成虚拟栅极间隔物，在虚拟栅极图案的两侧上形成鳍状有源图案中的凹槽，并在虚拟栅极图案的两侧形成源区和漏极区。

公开(公告)号：US20170077097A1

公开(公告)日：2017-03-16

申请号：US15010327

申请日：2016-01-29

申请人： YAOQI DONG ,  Mun Hyeon Kim ,  Keun Hwi Cho ,  Shigenobu Maeda ,  Han Su Oh

发明人： YAOQI DONG ,  Mun Hyeon Kim ,  Keun Hwi Cho ,  Shigenobu Maeda ,  Han Su Oh

IPC分类号： H01L27/092 ,  H01L29/161 ,  H01L23/535 ,  H01L29/49 ,  H01L29/78 ,  H01L29/08 ,  H01L29/165

CPC分类号： H01L23/535 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： Provided is a semiconductor device having first and second gate electrodes. The semiconductor device includes a substrate, an active region extending in a first direction on the substrate, a first gate electrode crossing the active region and extending in a second direction, and a second gate electrode extending in the second direction on the first gate electrode, wherein the first gate electrode has a first width in the first direction, and wherein the second gate electrode has a second width in the first direction, the second width being less than the first width.

摘要翻译： 提供了具有第一和第二栅电极的半导体器件。 半导体器件包括衬底，在衬底上沿第一方向延伸的有源区，与有源区交叉并沿第二方向延伸的第一栅极，以及在第一栅电极上沿第二方向延伸的第二栅电极， 其中所述第一栅极具有在所述第一方向上的第一宽度，并且其中所述第二栅极具有在所述第一方向上的第二宽度，所述第二宽度小于所述第一宽度。

公开(公告)号：US20160155816A1

公开(公告)日：2016-06-02

申请号：US15001499

申请日：2016-01-20

申请人： Shigenobu Maeda ,  Tsukasa Matsuda ,  Hidenobu Fukutome

发明人： Shigenobu Maeda ,  Tsukasa Matsuda ,  Hidenobu Fukutome

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16

CPC分类号： H01L29/665 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： A semiconductor device is provided. The semiconductor device includes a first fin on a substrate, a first gate electrode formed on the substrate to intersect the first fm, a first elevated source/drain on the first fin on both sides of the first gate electrode, and a first metal alloy layer on an upper surface and sidewall of the first elevated source/drain.

摘要翻译： 提供半导体器件。 所述半导体器件包括：衬底上的第一鳍片，形成在所述衬底上以与所述第一fm相交的第一栅极电极，所述第一栅电极两侧的所述第一鳍片上的第一升高源极/漏极，以及第一金属合金层 在第一升高的源极/漏极的上表面和侧壁上。

公开(公告)号：US08816440B2

公开(公告)日：2014-08-26

申请号：US12984261

申请日：2011-01-04

申请人： Shigenobu Maeda ,  Jeong Hwan Yang

发明人： Shigenobu Maeda ,  Jeong Hwan Yang

IPC分类号： H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/0922 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/1052 ,  H01L29/0649 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848

摘要： In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate. For example, mechanical stress can be applied to devices that operate in high-speed digital settings, while devices that operate in analog or RF signal settings, in which electrical noise such as flicker noise that may be introduced by applied stress may degrade performance, have no stress applied.

摘要翻译： 在其中使用NMOS器件和PMOS器件的半导体器件中，以不同的模式（例如模拟和数字模式）来执行应力工程，根据所需的操作模式，对特定器件有选择地施加应力工程。 也就是说，适当的机械应力，即拉伸或压缩，可以施加到和/或从设备（即，NMOS和/或PMOS器件）中去除和/或从器件去除，不仅基于它们的导电类型，即n型或p- 类型，而且还在于其预期的操作应用，例如模拟/数字，低电压/高电压，高速/低速，噪声敏感/噪声不敏感等。结果是个体的性能 设备根据其运行模式进行优化。 例如，机械应力可以应用于在高速数字设置中工作的设备，而在模拟或RF信号设置中工作的设备，其中可能由施加的应力引入的诸如闪烁噪声的电噪声可能降低性能，具有 没有施加应力。

公开(公告)号：US07531878B2

公开(公告)日：2009-05-12

申请号：US11610932

申请日：2006-12-14

申请人： Shigenobu Maeda ,  Shigeto Maegawa ,  Takuji Matsumoto

发明人： Shigenobu Maeda ,  Shigeto Maegawa ,  Takuji Matsumoto

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L29/045 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1087 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78615 ,  H01L29/78621 ,  H01L29/78654 ,  H01L29/78687 ,  H01L29/78696

摘要： There is provided a semiconductor device which is formed on a semiconductor substrate and allows effective use of the feature of the semiconductor substrate, and there is also provided a method of manufacturing the same. An N-channel MOS transistor including a P-type body layer (3a), and a P-type active layer (6) for body voltage application which is in contact with the P-type body layer (3a) are formed on an SOI substrate which is formed to align a crystal direction of a support substrate (1) with a crystal direction of an SOI layer (3). A path connecting the P-type body layer (3a) and the P-type active layer (6) for body voltage application is aligned parallel to the crystal direction of the SOI layer (3). Since hole mobility is higher in the crystal direction, parasitic resistance (Ra, Rb) can be reduced in the above path. This speeds up voltage transmission to the P-type body layer (3a) and improves voltage fixing capability in the P-type body layer (3a).

摘要翻译： 提供一种半导体器件，其形成在半导体衬底上并且有效地利用了半导体衬底的特征，并且还提供了一种制造该半导体衬底的方法。 包括P型体层（3a）和与P型体层（3a）接触的体电压施加用P型有源层（6）的N沟道MOS晶体管形成在SOI 衬底，其被形成为使支撑衬底（1）的<110>晶体方向与SOI层（3）的<100>晶体方向对准。 连接P型体层（3a）和用于体电压施加的P型有源层（6）的路径平行于SOI层（3）的<100>晶体方向排列。 由于在<100>晶体方向的空穴迁移率较高，所以在上述路径中可以减小寄生电阻（Ra，Rb）。 这加快了P型体层（3a）的电压传输，提高了P型体层（3a）的电压固定能力。

公开(公告)号：US07456464B2

公开(公告)日：2008-11-25

申请号：US11621177

申请日：2007-01-09

申请人： Shigenobu Maeda ,  Hiroyuki Takashino ,  Toshihide Oka

发明人： Shigenobu Maeda ,  Hiroyuki Takashino ,  Toshihide Oka

IPC分类号： H01L29/94

CPC分类号： H01L21/26586 ,  H01L21/74 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/0808 ,  H01L27/0811 ,  H01L27/1203 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/94

摘要： It is an object to obtain a semiconductor device having such a structure that respective electrical characteristics of an insulated gate type transistor and an insulated gate type capacitance are not deteriorated and a method of manufacturing the semiconductor device. An NMOS transistor Q1 and a PMOS transistor Q2 which are formed in an NMOS formation region A1 and a PMOS formation region A2 respectively have P−pocket regions 17 and N−pocket regions 27 in vicinal regions of extension portions 14e and 24e of N+ source-drain regions 14 and P+source-drain regions 24, respectively. On the other hand, an N-type variable capacitance C1 and a P-type variable capacitance C2 which are formed in an N-type variable capacitance formation region A3 and a P-type variable capacitance formation region A4 respectively do not have a region of a reverse conductivity type which is adjacent to extraction electrode regions corresponding to the P−pocket regions 17 and the N−pocket regions 27.

摘要翻译： 本发明的目的是获得具有绝缘栅型晶体管和绝缘栅型电容的各自电特性不劣化的结构的半导体器件以及半导体器件的制造方法。 形成在NMOS形成区域A 1和PMOS形成区域A 2中的NMOS晶体管Q 1和PMOS晶体管Q 2分别具有P 0〜 分别为N +源极 - 漏极区域14和P +源极 - 漏极区域24的延伸部分14e和24e的连续区域中的多个区域27。 另一方面，形成在N型可变电容形成区域A 3和P型可变电容形成区域A 4中的N型可变电容C 1和P型可变电容C 2分别不 具有与对应于凹穴区域17和凹陷区域27的引出电极区域相邻的反向导电型区域。

公开(公告)号：US07439587B2

公开(公告)日：2008-10-21

申请号：US11677956

申请日：2007-02-22

申请人： Yuuichi Hirano ,  Shigeto Maegawa ,  Toshiaki Iwamatsu ,  Takuji Matsumoto ,  Shigenobu Maeda ,  Yasuo Yamaguchi

发明人： Yuuichi Hirano ,  Shigeto Maegawa ,  Toshiaki Iwamatsu ,  Takuji Matsumoto ,  Shigenobu Maeda ,  Yasuo Yamaguchi

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21), a complete isolation portion (23) reaching an upper surface of an insulating film (3) is formed in the isolation insulating film (5). In other words, a semiconductor device comprises a complete-isolation insulating film which is so formed as to extend from the upper surface of the silicon layer (4) and reach the upper surface of insulating film (3) below the power supply line (21). With this structure, it is possible to obtain the semiconductor device capable of suppressing variation in potential of a body region caused by variation in potential of the power supply line.

摘要翻译： 在硅层（4）的上表面中选择性地形成部分沟槽型隔离绝缘膜（5）。 电源线（21）形成在隔离绝缘膜（5）的上方。 在电源线（21）的下方，在隔离绝缘膜（5）上形成到达绝缘膜（3）的上表面的完全隔离部（23）。 换句话说，半导体器件包括完全隔离绝缘膜，其形成为从硅层（4）的上表面延伸并到达电源线（21）下方的绝缘膜（3）的上表面 ）。 利用这种结构，可以获得能够抑制由电源线的电位变化引起的体区的电位变化的半导体器件。

公开(公告)号：US20080099786A1

公开(公告)日：2008-05-01

申请号：US12004290

申请日：2007-12-20

申请人： Shigenobu Maeda ,  Jeong Yang

发明人： Shigenobu Maeda ,  Jeong Yang

IPC分类号： H01L27/092

CPC分类号： H01L27/0922 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/1052 ,  H01L29/0649 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848

摘要： In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate. For example, mechanical stress can be applied to devices that operate in high-speed digital settings, while devices that operate in analog or RF signal settings, in which electrical noise such as flicker noise that may be introduced by applied stress may degrade performance, have no stress applied.

摘要翻译： 在其中使用NMOS器件和PMOS器件的半导体器件中，以不同的模式（例如模拟和数字模式）来执行应力工程，根据所需的操作模式，对特定器件有选择地施加应力工程。 也就是说，适当的机械应力，即拉伸或压缩，可以施加到和/或从设备（即，NMOS和/或PMOS器件）中去除和/或从器件去除，不仅基于它们的导电类型，即n型或p- 类型，而且还在于其预期的操作应用，例如模拟/数字，低电压/高电压，高速/低速，噪声敏感/噪声不敏感等。结果是个体的性能 设备根据其运行模式进行优化。 例如，机械应力可以应用于在高速数字设置中工作的设备，而在模拟或RF信号设置中工作的设备，其中可能由施加的应力引入的诸如闪烁噪声的电噪声可能降低性能，具有 没有施加应力。

公开(公告)号：US20080032486A1

公开(公告)日：2008-02-07

申请号：US11868143

申请日：2007-10-05

申请人： Toshiaki Iwamatsu ,  Shigenobu Maeda

发明人： Toshiaki Iwamatsu ,  Shigenobu Maeda

IPC分类号： H01L21/30

CPC分类号： H01L21/76243 ,  H01L21/02027 ,  H01L21/67092 ,  H01L21/68 ,  H01L21/76254 ,  H01L21/76256 ,  H01L23/544 ,  H01L29/045 ,  H01L29/78606 ,  H01L29/78654 ,  H01L29/78696 ,  H01L2223/54453 ,  H01L2223/54493 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor wafer manufacturing method comprising the steps of preparing a first semiconductor wafer having a plurality of cuts formed at edge portions in crystal directions, preparing a second semiconductor wafer having a cut formed at an edge portion in a crystal direction that is different from the crystal direction of one of said plurality of cuts of said first semiconductor wafer, bonding said first and second semiconductor wafers to each other while using said one of said plurality of cuts of said first semiconductor wafer and said cut of said second semiconductor wafer in order to position said first and second semiconductor wafers, with another one of said plurality of cuts of said first semiconductor wafer being engaged with a guide portion of a semiconductor wafer manufacturing apparatus, thinning said first semiconductor wafer, implanting oxygen ions from said first semiconductor wafer side into a neighborhood of a part where said first and second semiconductor wafers are bonded to each other, and forming the portion implanted with the oxygen ions into an oxide film layer by a thermal treatment.

摘要翻译： 一种半导体晶片制造方法，包括以下步骤：制备在晶体方向上形成有多个切口的第一半导体晶片，所述第一半导体晶片具有在晶体方向上不同晶体的边缘部分处形成的切口的第二半导体晶片 所述第一半导体晶片的所述多个切口中的一个切口的方向，将所述第一和第二半导体晶片彼此接合，同时使用所述第一半导体晶片的所述多个切口和所述第二半导体晶片的所述切口中的所述一个切口以便定位 所述第一和第二半导体晶片，所述第一半导体晶片的所述多个切口中的另一个与半导体晶片制造设备的引导部分接合，使所述第一半导体晶片变薄，将氧离子从所述第一半导体晶片侧注入到 所述第一和第二半导体晶片的部分附近 e彼此键合，并且通过热处理将注入氧离子的部分形成氧化物膜层。