公开(公告)号：US20220077061A1

公开(公告)日：2022-03-10

申请号：US17015816

申请日：2020-09-09

申请人： NANYA TECHNOLOGY CORPORATION

发明人： CHUN-CHENG LIAO

IPC分类号： H01L23/535 ,  H01L23/532 ,  H01L21/768 ,  H01L27/108

摘要： The present disclosure relates to a semiconductor device with a composite landing pad. The semiconductor device includes a first dielectric layer disposed over a semiconductor substrate. The semiconductor device also includes a lower metal plug and a barrier layer disposed in the first dielectric layer. The lower metal plug is surrounded by the barrier layer. The semiconductor device further includes an inner silicide portion disposed over the lower metal plug, and an outer silicide portion disposed over the barrier layer. A topmost surface of the outer silicide portion is higher than a topmost surface of the inner silicide portion.

公开(公告)号：US20230395489A1

公开(公告)日：2023-12-07

申请号：US17830482

申请日：2022-06-02

申请人： NANYA TECHNOLOGY CORPORATION

发明人： CHUN-CHENG LIAO

IPC分类号： H01L23/522 ,  H01L25/065 ,  H01L23/00 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L23/5226 ,  H01L2224/08147 ,  H01L24/05 ,  H01L24/08 ,  H01L24/06 ,  H01L23/5283 ,  H01L23/53266 ,  H01L23/53214 ,  H01L23/53228 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2224/06139 ,  H01L2224/06051 ,  H01L2224/0603 ,  H01L2224/05073 ,  H01L2224/05017 ,  H01L2224/05557 ,  H01L2224/02375 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L25/0652

摘要： The present application discloses a semiconductor device. The semiconductor device includes a first chip including a first substrate, a first redistribution layer above the first substrate, a first lower bonding pad positioned on the first redistribution layer, and a second lower bonding pad above the first substrate; and a second chip including a dense region and a loose region adjacent to the dense region, upper pads on the first lower bonding pad and the second lower bonding pad, second redistribution layers on the upper pads, and a first redistribution plug and a second redistribution plug respectively and correspondingly on the second redistribution layers. The first redistribution plug is at the dense region and includes a first aspect ratio. The second redistribution plug is at the loose region and includes a second aspect ratio less than the first aspect ratio.

公开(公告)号：US20230395427A1

公开(公告)日：2023-12-07

申请号：US17830442

申请日：2022-06-02

申请人： NANYA TECHNOLOGY CORPORATION

发明人： CHUN-CHENG LIAO

IPC分类号： H01L21/768 ,  H01L23/00

CPC分类号： H01L21/76816 ,  H01L24/80 ,  H01L24/03 ,  H01L21/76879 ,  H01L21/7684 ,  H01L23/5226

摘要： The present application discloses a method for fabricating a semiconductor device. The method includes providing a first chip comprising a first substrate, a first redistribution layer positioned above the first substrate, a first lower bonding pad positioned on the first redistribution layer, and a second lower bonding pad positioned above the first substrate and distant from the first lower bonding pad. The method also includes providing a second chip comprising a dense region and a loose region adjacent to the dense region; a plurality of upper pads positioned on the first lower bonding pad and the second lower bonding pad; and a plurality of second redistribution layers positioned on the plurality of upper pads. The method further performs bonding the second chip onto the first chip in a face-to-face manner, wherein the plurality of upper pads contact the first lower bonding pad and the second lower bonding pad.

公开(公告)号：US20220059544A1

公开(公告)日：2022-02-24

申请号：US17516671

申请日：2021-11-01

申请人： NANYA TECHNOLOGY CORPORATION

发明人： CHUN-CHENG LIAO

IPC分类号： H01L27/108 ,  H01L23/532 ,  H01L29/49 ,  H01L21/762 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L49/02

摘要： The present disclosure provides a method for preparing a semiconductor memory device with air gaps between conductive features. The method includes forming an isolation layer defining a first active region in a substrate; forming a first doped region in the first active region; forming a first word line buried in a first trench adjacent to the first doped region; and forming a high-level bit line contact positioned on the first doped region; forming a first air gap surrounding the high-level bit line contact. The forming of the first word line comprises: forming a lower electrode structure and an upper electrode structure on the lower electrode structure. The forming of the upper electrode structure comprises: forming a source layer substantially covering a sidewall of the first trench; forming a conductive layer on the source layer; and forming a work-function adjustment layer disposed between the source layer and the conductive layer.

公开(公告)号：US20240047400A1

公开(公告)日：2024-02-08

申请号：US18381895

申请日：2023-10-19

申请人： NANYA TECHNOLOGY CORPORATION

发明人： CHUN-CHENG LIAO

IPC分类号： H01L23/00 ,  H01L23/31

CPC分类号： H01L24/16 ,  H01L24/13 ,  H01L24/05 ,  H01L23/3171 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/11011 ,  H01L2224/16147 ,  H01L2224/13582 ,  H01L2224/13006 ,  H01L2224/02235 ,  H01L2224/13017

摘要： A semiconductor device includes a conductive pattern formed over a semiconductor substrate, and an interconnect structure formed over the conductive pattern, wherein the interconnect structure includes a graphene liner. The semiconductor device also includes an interconnect liner formed between the interconnect structure and the conductive pattern and surrounding the interconnect structure. The inner sidewall surfaces of the interconnect liner are in direct contact with the interconnect structure, and a maximum distance between outer sidewall surfaces of the interconnect liner is greater than a width of the conductive pattern. The semiconductor device further includes a semiconductor die bonded to the semiconductor substrate. The semiconductor die includes a conductive pad facing the interconnect structure, wherein the conductive pad is electrically connected to the conductive pattern.

公开(公告)号：US20230268303A1

公开(公告)日：2023-08-24

申请号：US17675042

申请日：2022-02-18

申请人： NANYA TECHNOLOGY CORPORATION

发明人： CHUN-CHENG LIAO

IPC分类号： H01L23/00 ,  H01L23/31

CPC分类号： H01L24/16 ,  H01L24/13 ,  H01L24/05 ,  H01L23/3171 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/16147 ,  H01L2224/13582 ,  H01L2224/13006 ,  H01L2224/02235 ,  H01L2224/13017 ,  H01L2224/11011

摘要： A semiconductor device includes a conductive pattern formed over a semiconductor substrate, and an interconnect structure formed over the conductive pattern, wherein the interconnect structure includes a graphene liner. The semiconductor device also includes an interconnect liner formed between the interconnect structure and the conductive pattern and surrounding the interconnect structure. The inner sidewall surfaces of the interconnect liner are in direct contact with the interconnect structure, and a maximum distance between outer sidewall surfaces of the interconnect liner is greater than a width of the conductive pattern. The semiconductor device further includes a semiconductor die bonded to the semiconductor substrate. The semiconductor die includes a conductive pad facing the interconnect structure, wherein the conductive pad is electrically connected to the conductive pattern.

公开(公告)号：US20230141895A1

公开(公告)日：2023-05-11

申请号：US17520991

申请日：2021-11-08

申请人： NANYA TECHNOLOGY CORPORATION

发明人： CHUN-CHENG LIAO

IPC分类号： H01L21/768 ,  H01L23/522

CPC分类号： H01L21/76897 ,  H01L21/7685 ,  H01L21/76885 ,  H01L23/5226 ,  H01L21/76864

摘要： A method for preparing a semiconductor device structure includes forming a first dielectric layer over a semiconductor substrate; forming a first conductive plug in the first dielectric layer; forming a polysilicon layer covering the first dielectric layer and the first conductive plug; transforming a portion of the polysilicon layer into a silicide portion; forming a second conductive plug directly over the silicide portion; and forming a second dielectric layer surrounding the second conductive plug.

公开(公告)号：US20220108952A1

公开(公告)日：2022-04-07

申请号：US17551432

申请日：2021-12-15

申请人： NANYA TECHNOLOGY CORPORATION

发明人： CHUN-CHENG LIAO

IPC分类号： H01L23/535 ,  H01L23/532 ,  H01L21/768 ,  H01L27/108

摘要： The present disclosure relates to method for preparing a semiconductor device with a composite landing pad. The method includes forming a first dielectric layer over a semiconductor substrate. The semiconductor device also includes forming a lower metal plug and a barrier layer in the first dielectric layer. The lower metal plug is surrounded by the barrier layer. The semiconductor device further includes forming an inner silicide portion over the lower metal plug, and an outer silicide portion over the barrier layer. A topmost surface of the outer silicide portion is higher than a topmost surface of the inner silicide portion.