公开(公告)号：US20240258258A1

公开(公告)日：2024-08-01

申请号：US18103698

申请日：2023-01-31

申请人： Taiwan Semiconductor Manufacturing Company

发明人： Shih-Cheng Chang ,  Yao-Chun Chuang

IPC分类号： H01L23/00

CPC分类号： H01L24/11 ,  H01L24/10 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/11011 ,  H01L2224/11334 ,  H01L2224/1182 ,  H01L2224/11849 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/1357 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/1369 ,  H01L2224/1413 ,  H01L2224/14505 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81201 ,  H01L2224/81815 ,  H01L2924/014 ,  H01L2924/20107

摘要： A substrate or IC chip is connected with a second substrate or IC chip. This entails disposing electrically conductive balls on electrical bonding pads of a surface of the substrate or IC chip to form a ball grid array (BGA) disposed on the surface of the substrate or IC chip, and electrically and mechanically connecting the surface of the substrate or IC chip to the second substrate or IC chip using the BGA. An underfill material may be disposed on the surface of the substrate or IC chip around bonds between the balls and the electrical bonding pads. There may be at least two different types of electrically conductive balls in the BGA, such as solder balls and copper-based balls.

公开(公告)号：US20240047397A1

公开(公告)日：2024-02-08

申请号：US18123794

申请日：2023-03-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Bo-Yu CHIU ,  Pei-Wei LEE ,  Fu Wei LIU ,  Yun-Chung WU ,  Hao Chun YANG ,  Chin-Yu KU ,  Ming-Da CHENG ,  Ming-Ji LII

IPC分类号： H01L23/00

CPC分类号： H01L24/13 ,  H01L24/05 ,  H01L2224/02235 ,  H01L2224/10122 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05147 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/11011

摘要： A semiconductor device includes a substrate, one or more wiring layers disposed over the substrate, a passivation layer disposed over the one or more wiring layers, a first conductive layer disposed over the passivation layer, a second conductive layer disposed over the first conductive layer, an isolation structure formed in the first and second conductive layers to isolate a part of the first and second conductive layers, and a first metal pad disposed over the isolation structure and the part of the first and second conductive layers. In one or more of the foregoing or following embodiments, the semiconductor device further includes a second metal pad disposed over the second conductive layer and electrically isolated from the first metal pad.

公开(公告)号：US20230386950A1

公开(公告)日：2023-11-30

申请号：US18142416

申请日：2023-05-02

申请人： SJ Semiconductor(Jiangyin) Corporation

发明人： Yenheng Chen ,  Chengchung Lin

IPC分类号： H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29

CPC分类号： H01L23/3128 ,  H01L21/56 ,  H01L24/11 ,  H01L24/17 ,  H01L24/03 ,  H01L24/09 ,  H01L23/293 ,  H01L2224/14104 ,  H01L2224/02381 ,  H01L2224/02379 ,  H01L2224/11011 ,  H01L2224/14131 ,  H01L2224/02333 ,  H01L2224/03 ,  H01L2224/06505

摘要： A 3D fan-out packaging structure of an interconnection system with ultra-high density and a method for manufacturing the same are disclosed; the packaging structure includes a first insulating layer, first metal solder pads, a metal pillar, a first chip, a second insulating layer, second metal solder pads, a first encapsulating layer, a first rewiring layer, a second chip, a second encapsulating layer, a second rewiring layer, and a solder ball. The packaging structure adopts the “RDL first” process, and non-soldering interfaces between the first and second metal solder pads help achieve bonding with a spacing of 5-10 μm or even less, much smaller than conventional soldering spacings, thus increasing the number of available I/O ports and obtaining a high-density, highly integrated packaging structure. In addition, in the present disclosure, various chips and electronic components can be integrated together, thereby achieving high-performance system-level packaging with higher flexibility and compatibility.

公开(公告)号：US10014218B1

公开(公告)日：2018-07-03

申请号：US15492525

申请日：2017-04-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Meng-Fu Shih ,  Cheng-Lin Huang ,  Chien-Chen Li ,  Che-Jung Chu ,  Wen-Ming Chen ,  Kuo-Chio Liu

IPC分类号： H01L23/48 ,  H01L21/78 ,  H01L23/00 ,  H01L23/544 ,  H01L21/56 ,  H01L23/522 ,  H01L21/768

CPC分类号： H01L21/76879 ,  H01L21/486 ,  H01L21/561 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/544 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/97 ,  H01L2223/5446 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/11011 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13011 ,  H01L2224/13013 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14131 ,  H01L2224/16146 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/3003 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/92 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L21/304

摘要： A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor structure. The semiconductor structure has a central portion and a peripheral portion surrounding the central portion. The method includes forming first conductive bumps and dummy conductive bumps over a surface of the semiconductor structure. The first conductive bumps are over the central portion and electrically connected to the semiconductor structure. The dummy conductive bumps are over the peripheral portion and electrically insulated from the semiconductor structure. The first conductive bumps each have a first thickness and a first width. The dummy conductive bumps each have a second thickness and a second width. The second thickness is less than the first thickness. The second width is greater than the first width.

公开(公告)号：US09853004B2

公开(公告)日：2017-12-26

申请号：US15296286

申请日：2016-10-18

申请人： Invensas Corporation

发明人： Cyprian Emeka Uzoh

IPC分类号： H01L21/768 ,  H01L23/00 ,  H01L25/00 ,  H01L23/48

CPC分类号： H01L24/02 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L25/00 ,  H01L2224/02166 ,  H01L2224/02372 ,  H01L2224/05548 ,  H01L2224/11 ,  H01L2224/11011 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/16152 ,  Y10T29/49165 ,  H01L2924/00

摘要： An apparatus relating generally to a substrate is disclosed. In this apparatus, a post extends from the substrate. The post includes a conductor member. An upper portion of the post extends above an upper surface of the substrate. An exterior surface of the post associated with the upper portion is in contact with a dielectric layer. The dielectric layer is disposed on the upper surface of the substrate and adjacent to the post to provide a dielectric collar for the post. An exterior surface of the dielectric collar is in contact with a conductor layer. The conductor layer is disposed adjacent to the dielectric collar to provide a metal collar for the post, where a top surface of each of the conductor member, the dielectric collar and the metal collar have formed thereon a bond structure for interconnection of the metal collar and the conductor member.

公开(公告)号：US20170047304A1

公开(公告)日：2017-02-16

申请号：US14823021

申请日：2015-08-11

申请人： LENOVO ENTERPRISE SOLUTIONS (SINGAPORE) PTE. LTD.

发明人： JOSEPH KUCZYNSKI ,  MELISSA K. MILLER ,  HEIDI D. WILLIAMS ,  JING ZHANG

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  B23K1/00 ,  H05K3/34

CPC分类号： H01L24/17 ,  B23K1/0016 ,  B23K3/0623 ,  H01L23/3142 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/11011 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16227 ,  H01L2224/81007 ,  H01L2224/81815 ,  H01L2924/06 ,  H01L2924/14 ,  H01L2924/1531 ,  H05K3/341 ,  H05K3/3436 ,  H05K2201/10734 ,  H05K2201/10977 ,  Y02P70/613

摘要： Example methods, apparatus, and products for creating an environmentally protective coating for integrated circuit assemblies are described herein. A preform plastic sheet is places over components of an integrated circuit such that during a reflow process, the preform plastic sheet melts to form a conformal coating over components of the integrated circuit assembly.

摘要翻译： 本文描述了用于为集成电路组件创建环境保护涂层的示例性方法，设备和产品。 预成型塑料片位于集成电路的部件之上，使得在回流工艺期间，预制塑料片熔化以在集成电路组件的部件上形成共形涂层。

公开(公告)号：US20150340349A1

公开(公告)日：2015-11-26

申请号：US14819189

申请日：2015-08-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Mirng-Ji Lii ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Kai-Chiang Wu

IPC分类号： H01L25/10 ,  H01L25/00 ,  H01L23/31 ,  H01L25/065

CPC分类号： H01L24/14 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/11011 ,  H01L2224/14 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0206 ,  H05K1/0306 ,  H05K1/113 ,  H05K2201/068 ,  H01L2224/45099 ,  H01L2924/00012

摘要： A package on packaging structure comprising a first package and a second package provides for improved thermal conduction and mechanical strength by the introduction of a thermally conductive substrate attached to the second package. The first package has a first substrate and a first integrated circuit. The second package has a second substrate containing through vias that has a first coefficient of thermal expansion. The second package also has a second integrated circuit having a second coefficient of thermal expansion located on the second substrate. The second coefficient of thermal expansion deviates from the first coefficient of thermal expansion by less than about 10 or less than about 5 parts-per-million per degree Celsius. A first set of conductive elements couples the first substrate and the second substrate. A second set of conductive elements couples the second substrate and the second integrated circuit.

摘要翻译： 包装结构包括第一包装和第二包装通过引入连接到第二包装件上的导热基材提供改进的热传导和机械强度。 第一封装具有第一衬底和第一集成电路。 第二包装具有包含通孔的第二基板，其具有第一热膨胀系数。 第二封装还具有第二集成电路，其具有位于第二基板上的第二热膨胀系数。 第二热膨胀系数从第一热膨胀系数偏离每摄氏度小于约10或小于约5百万分之一。 第一组导电元件将第一基板和第二基板连接。 第二组导电元件将第二基板和第二集成电路耦合。

公开(公告)号：US09095081B1

公开(公告)日：2015-07-28

申请号：US14663806

申请日：2015-03-20

申请人： International Business Machines Corporation

发明人： Peter A. Gruber ,  Paul A. Lauro ,  Jae-Woong Nah

IPC分类号： H01L21/00 ,  H05K3/34 ,  H05K13/04

CPC分类号： H05K3/3436 ,  B23K1/0016 ,  B23K3/0638 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/11011 ,  H01L2224/13076 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16113 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81065 ,  H01L2224/81193 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/14 ,  H01L2924/20104 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/35 ,  H05K3/3494 ,  H05K13/0465 ,  H05K2203/043 ,  H01L2924/00014 ,  H01L2924/014

摘要： Multiple injections of molten solder are employed to form double solder bumps having outer layers that melt at lower temperatures than the inner portions thereof. During a flip chip assembly process, the reflow temperature is above the melting temperature of the outer layers and below the melting temperature of the inner portions of the solder bumps. As the inner portions of the solder bumps do not collapse during reflow, a flip chip assembly can be made at relatively low temperatures and have a high stand-off height. A structure having double solder bumps facilitates flip chip assembly.

摘要翻译： 采用多次注入熔融焊料来形成双层焊料凸点，其外层在比其内部部分更低的温度下熔化。 在倒装芯片组装过程中，回流温度高于外层的熔化温度并低于焊料凸块的内部部分的熔化温度。 由于焊料凸块的内部在回流期间不会塌陷，所以可以在相对低的温度下制造倒装芯片组件并具有高的间隔高度。 具有双重焊料凸块的结构有助于倒装芯片组装。

公开(公告)号：US08956966B2

公开(公告)日：2015-02-17

申请号：US14447336

申请日：2014-07-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yung-Chi Lin ,  Hsin-Yu Chen ,  Wen-Chih Chiou ,  Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Jing-Cheng Lin

IPC分类号： H01L21/44 ,  H01L21/768 ,  H01L23/00

CPC分类号： H01L23/49827 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/0557 ,  H01L2224/11011 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/1405 ,  H01L2224/14104 ,  H01L2224/73204 ,  H01L2924/01028 ,  H01L2924/0132 ,  H01L2924/067 ,  H01L2924/0705 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00012

摘要： A device includes a substrate having a front side and a backside, a through-via extending from the backside to the front side of the substrate, and a conductive pad on the backside of the substrate and over the through-via. The conductive pad has a substantially planar top surface. A conductive bump has a non-planar top surface over the substantially planar top surface and aligned to the through-via. The conductive bump and the conductive pad are formed of a same material. No interface is formed between the conductive bump and the conductive pad.

摘要翻译： 一种器件包括具有正面和背面的衬底，从衬底的背面延伸到前侧的通孔，以及位于衬底的背面和通孔上方的导电焊盘。 导电垫具有基本平坦的顶表面。 导电凸块在基本上平坦的顶表面上方具有非平面的顶表面，并且与通孔对准。 导电凸块和导电垫由相同的材料形成。 在导电凸块和导电垫之间不形成界面。

公开(公告)号：US20110233740A1

公开(公告)日：2011-09-29

申请号：US13155203

申请日：2011-06-07

申请人： Matt E. Schwab ,  J. Michael Brooks ,  David J. Corisis

发明人： Matt E. Schwab ,  J. Michael Brooks ,  David J. Corisis

IPC分类号： H01L23/495 ,  H01L21/58 ,  H01L21/60 ,  H01L23/488

CPC分类号： H01L24/03 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/09 ,  H01L24/17 ,  H01L24/28 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/0401 ,  H01L2224/11011 ,  H01L2224/13111 ,  H01L2224/1405 ,  H01L2224/16225 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/85 ,  H01L2224/92125 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a method for forming a microelectronic device includes attaching a microelectronic die to a support member by forming an attachment feature on at least one of a back side of the microelectronic die and the support member. The attachment feature includes a volume of solder material. The method also includes contacting the attachment feature with the other of the microelectronic die and the support member, and reflowing the solder material to join the back side of the die and the support member via the attachment feature. In several embodiments, the attachment feature is not electrically connected to internal active structures of the die.

摘要翻译： 公开了用于制造封装的微电子器件的封装的微电子器件和方法。 在一个实施例中，用于形成微电子器件的方法包括通过在微电子管芯的背面和支撑构件的至少一个上形成附着特征来将微电子管芯附接到支撑构件。 附件特征包括一定量的焊料。 该方法还包括使附接特征与另一个微电子管芯和支撑构件接触，以及回流焊料材料以经由附接特征连接到管芯的背面和支撑构件。 在几个实施例中，附接特征不与管芯的内部有源结构电连接。