公开(公告)号：US20240365530A1

公开(公告)日：2024-10-31

申请号：US18764368

申请日：2024-07-05

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Tseng-Fu LU ,  Chuan-Lin HSIAO

IPC分类号： H10B12/00 ,  H01L21/762 ,  H01L29/06

CPC分类号： H10B12/315 ,  H01L21/762 ,  H01L29/0649 ,  H10B12/03 ,  H10B12/482 ,  H10B12/488

摘要： A memory structure includes a substrate, a first word line and a first word line. The substrate has a plurality of active areas and an isolation structure surrounding the active areas. The first word line trench is formed across a first active area of the active areas and the isolation structure. The first word line trench includes a first slot and a first groove. The first slot is recessed from a top surface of the substrate. The first groove expands from a bottom of the first slot. A first sidewall is connected between the bottom of the first slot and a top of the first groove. A first word line is formed in the first word line trench. The first word line comprises a gate dielectric conformally formed on the first groove and the first slot.

公开(公告)号：US20240047265A1

公开(公告)日：2024-02-08

申请号：US18484452

申请日：2023-10-11

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Chuan-Lin HSIAO ,  Wei-Ming LIAO

IPC分类号： H01L21/762 ,  H01L29/06

CPC分类号： H01L21/76237 ,  H01L29/0638 ,  H01L29/0649 ,  H10B12/00

摘要： A manufacturing method of a semiconductor structure includes: etching a substrate such that the substrate has a first top surface and a second top surface higher than the first top surface; implanting the first top surface of the substrate by boron to increase a p-type concentration of the first top surface of the substrate; forming a first dielectric layer on the substrate; and forming a second dielectric layer on the first dielectric layer.

公开(公告)号：US20230141995A1

公开(公告)日：2023-05-11

申请号：US17454616

申请日：2021-11-11

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Chuan-Lin HSIAO ,  Wei-Ming LIAO

IPC分类号： H01L21/762 ,  H01L29/06

CPC分类号： H01L21/76237 ,  H01L29/0649 ,  H01L29/0638 ,  H01L27/108

摘要： A manufacturing method of a semiconductor structure includes: etching a substrate such that the substrate has a first top surface and a second top surface higher than the first top surface; implanting the first top surface of the substrate by boron to increase a p-type concentration of the first top surface of the substrate; forming a first dielectric layer on the substrate; and forming a second dielectric layer on the first dielectric layer.

公开(公告)号：US20230262958A1

公开(公告)日：2023-08-17

申请号：US17651068

申请日：2022-02-15

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Tseng-Fu LU ,  Chuan-Lin HSIAO

IPC分类号： H01L27/108 ,  H01L29/06 ,  H01L21/762

CPC分类号： H01L27/10814 ,  H01L27/10891 ,  H01L27/10885 ,  H01L27/1085 ,  H01L29/0649 ,  H01L21/762

摘要： A memory structure includes a substrate, a first word line and a first word line. The substrate has a plurality of active areas and an isolation structure surrounding the active areas. The first word line trench is formed across a first active area of the active areas and the isolation structure. The first word line trench includes a first slot and a first groove. The first slot is recessed from a top surface of the substrate. The first groove expands from a bottom of the first slot. A first sidewall is connected between the bottom of the first slot and a top of the first groove. A first word line is formed in the first word line trench. The first word line comprises a gate dielectric confomally formed on the first groove and the first slot.

公开(公告)号：US20230197771A1

公开(公告)日：2023-06-22

申请号：US17552882

申请日：2021-12-16

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Chuan-Lin HSIAO

IPC分类号： H01L29/06 ,  H01L27/108 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L23/532 ,  H01L29/40

CPC分类号： H01L29/0607 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/4236 ,  H01L29/518 ,  H01L29/4916 ,  H01L23/53257 ,  H01L29/401

摘要： The present application provides a memory device having several word lines (WL) with reduced leakage and a manufacturing method of the memory device. The memory device includes a semiconductor substrate defined with an active area and including a recess extending into the semiconductor substrate; and a word line disposed within the recess, wherein the word line includes an insulating layer disposed within the recess, a conductive layer surrounded by the insulating layer, and a conductive member enclosed by the conductive layer, and the insulating layer includes a lining portion conformal to the recess and a protruding portion disposed above the conductive layer. A method of manufacturing the memory device is also disclosed.

公开(公告)号：US20230178614A1

公开(公告)日：2023-06-08

申请号：US17544410

申请日：2021-12-07

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Chuan-Lin HSIAO

IPC分类号： H01L29/423 ,  H01L27/108

CPC分类号： H01L29/4236 ,  H01L27/10823

摘要： The present disclosure provides a semiconductor device having a buried wordline. The semiconductor device includes a substrate having a surface and a first dielectric layer extending from the surface of the substrate into the substrate. The semiconductor device also includes a second dielectric layer disposed on the first dielectric layer and extending from the surface of the substrate into the substrate and a first conductive layer disposed in the substrate and separated from the substrate by the first dielectric layer and the second dielectric layer.