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    BIT LINE SENSE AMPLIFIER AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME
    3.
    发明申请
    BIT LINE SENSE AMPLIFIER AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME 有权

    公开(公告)号：US20230036684A1

    公开(公告)日：2023-02-02

    申请号：US17859153

    申请日：2022-07-07

    申请人： INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY

    发明人： Seong Ook JUNG ,  In Jun JUNG ,  Tae Hyun KIM

    IPC分类号： G11C11/4093 ,  G11C11/4094 ,  G11C11/408 ,  H03K19/017

    摘要： A bit line sense amplifier includes: a first inverter having an input terminal connected to a first sensing node and an output terminal connected to a second inner bit line; a second inverter having an input terminal connected to a second sensing node and an output terminal connected to a first inner bit line; a first capacitor connected between the first sensing node and the first inner bit line; a second capacitor connected between the second sensing node and the second inner bit line; an isolation unit configured to cut off a connection between the first inner bit line and a second bit line; and an offset cancellation unit configured to connect the first sensing node to the second inner bit line, the first inner bit line to the first bit line, the second sensing node to the first inner bit line, and the second inner bit line to the second bit line.